Wafer-Level Chip Failure Probability Prediction
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Solution Overview
Problem
Current methods cannot predict the failure probability of individual semiconductor chips based on wafer-level test measurements due to the loss of traceability between processes after the wafer is cut.
Innovation Solution
A method is developed to teach a machine learning system to predict failure probabilities of chips on a wafer by using a training dataset comprising wafer-level test measurements and associated final test yields, and then aggregating these predictions to minimize the difference between predicted and actual final test yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If wafer-level test measurements are used to predict chip failure, then early defect detection is enabled, but traceability between wafer-level measurements and final test results is lost after dicing
Solution Approach 1:
The patent performs wafer-level testing and records measurements before the dicing process occurs. By conducting the prediction action in advance of the cutting process, the system captures traceability information while it still exists, enabling early defect detection without losing the connection between wafer measurements and individual chip outcomes
Solution Approach 2:
The patent divides the wafer into individual chip segments and applies machine learning models to predict failure probabilities for each segment independently. This segmentation allows the system to maintain traceability at the chip level while still utilizing wafer-level measurement data, resolving the contradiction between early detection and information loss
2Measurement precision
If machine learning models are trained with wafer-level data, then prediction accuracy improves, but the complexity of the system increases
Solution Approach 1:
The patent introduces machine learning models as intermediary components that bridge wafer-level measurements and chip-level failure predictions. These models act as mediators that process aggregate wafer data and translate it into individual chip predictions, improving accuracy while managing system complexity through modular architecture
Solution Approach 2:
The patent transforms wafer-level measurement parameters into chip-level prediction parameters using machine learning. By changing the parameters from aggregate wafer statistics to individual chip failure probabilities, the system achieves higher prediction accuracy while the modular ML architecture keeps complexity manageable
3Productivity
If all chips are processed without selection, then manufacturing throughput is maintained, but waste increases due to defective chips
Solution Approach 1:
The patent performs failure probability prediction before final chip processing and packaging. By identifying defective chips in advance, the system can remove them from the production stream early, preventing waste while maintaining throughput of good chips. The preliminary prediction action enables selective processing without bottlenecking the overall manufacturing flow
Solution Approach 2:
The patent enables the discarding of predicted defective chips while recovering and continuing processing of chips with low failure probabilities. This selective discarding approach reduces waste of defective materials while maintaining high productivity by keeping good chips in the production stream
Data Source
AI summary
A method is for teaching a machine learning system to predict failure probabilities of chips on a wafer. The method is based on a prediction of final test yields depending on wafer-level test measurements by the machine learning system. The machine learning system predicts the failure probabilities of the chips depending on the wafer-level test measurements, and the predicted failure probabilities are aggregated to the predicted final test yields. The machine learning system is trained, such that a math difference between predicted final test yields and final test yields from a training data set is minimized. Differences between the predicted final test yields and final test yields from a training data set are minimized.