Wafer-Scale Chip Fill Pattern Layout for Uniform Die Performance
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Solution Overview
Problem
In wafer-scale chips, dies with the same design perform differently due to varying wafer topography across different locations, leading to performance variations.
Innovation Solution
A design method and system that perform wafer-level topography control by inserting customized patterns of fill shapes into die layouts to minimize across-wafer thickness variations, using a computer-aided design system to optimize wafer-level topography and generate a final chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple dies are formed on a semiconductor wafer at different locations, then wafer-scale chip processing speed is improved, but performance variations occur due to different wafer topography at those locations
Solution Approach 1:
The patent applies local quality by inserting different patterns of fill shapes into different dies based on their specific locations on the wafer. Each die receives a customized fill pattern that compensates for the local topography at its position, ensuring that all dies achieve consistent thickness and performance despite being formed at different locations with varying wafer topography.
Solution Approach 2:
The patent changes physical parameters by modifying the fill shape patterns in response to measured wafer topography variations. The system adjusts the fill insertion parameters (shape, size, distribution) based on the local thickness variations, thereby compensating for topography differences and achieving uniform die performance across the wafer.
2Reliability
If different patterns of fill shapes are inserted into die layouts to minimize across-wafer thickness variations, then performance consistency is improved, but design complexity increases
Solution Approach 1:
The patent applies preliminary action by measuring the wafer topography and determining the optimal fill patterns for each die location before the actual die fabrication process. This advance planning allows the system to pre-calculate and store the specific fill patterns needed for each die, eliminating the need for complex real-time adjustments during manufacturing and simplifying the production process.
Data Source
AI summary
Disclosed is a wafer-scale chip structure including a semiconductor wafer and multiple dies on the semiconductor wafer. The dies can include at least two dies with different patterns of fill shapes. Also disclosed are wafer-scale chip design methods and systems. In the design methods and systems, post-chip layout wafer-level topography optimization is performed to, for example, minimize performance variations between dies of the same design within the wafer-scale chip. Specifically, across-wafer die placement and wafer-level topography information is used to custom design and/or select different patterns of fill shapes to be inserted into the layouts of dies placed at different locations across the wafer-scale chip (including different patterns to be inserted into the layouts of dies that have the same design) in order to generate a design that minimizes either all across-wafer thickness variations or at least across-wafer thickness variations associated with specific dies having the same specific design.