Wafer-Level Chip Outlines Using Plasma and Blade Dicing
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Solution Overview
Problem
Current dicing methods for semiconductor wafers, such as blade dicing, laser dicing, and plasma dicing, face limitations in producing chips with complex shapes, suffer from productivity issues, and can cause damage or interference, particularly for ion trap devices where laser scattering is a concern.
Innovation Solution
A method combining plasma dicing to create complex shapes and blade dicing for straight-line cuts, with the option of processes like deposition and patterning without cooling gases, to produce semiconductor chips with varied outlines, including curved or bent lines, minimizing laser interference for ion trap applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If blade dicing is used, then simplicity of the dicing process is maintained, but chip shape is limited to simple rectangular or parallelogram forms
Solution Approach 1:
The dicing process is divided into two distinct stages: first, plasma dicing creates the complex curved outline shape of the chip, and second, blade dicing performs straight-line cuts to separate individual chips. This segmentation allows each method to perform its optimal function without compromise.
Solution Approach 2:
The patent combines two different dicing methods (plasma dicing and blade dicing) into a single manufacturing workflow. Plasma dicing handles the complex curved portions of the chip outline, while blade dicing handles the straight-line separations, merging their capabilities to achieve both shape complexity and manufacturing simplicity.
2Shape
If laser dicing is used, then complex shapes can be achieved, but productivity degrades for wafers with thickness of 100 μm or more and high heat is generated
Solution Approach 1:
The patent replaces laser dicing (optical method) with plasma dicing (chemical/physical method) for creating complex chip shapes. Plasma dicing avoids the heat generation and productivity degradation associated with laser dicing on thick wafers, while still achieving complex curved outlines through controlled plasma etching.
3Shape
If plasma dicing is used for deep Si etching, then complex shapes can be created, but additional protective layers are required which complicate the process
Solution Approach 1:
The patent applies plasma dicing selectively only for creating the curved outline portions of the chip shape, rather than using it for the entire dicing process. Straight-line cuts are performed using simpler blade dicing, thus avoiding the need for extensive protective layer deposition while still achieving complex chip shapes where needed.
4Productivity
If plasma dicing is performed before other processes, then wafer-level processing is enabled, but thin beam breakage generates fragments that damage chip surfaces and reduce yield
Solution Approach 1:
The dicing process is segmented into plasma dicing for outline creation followed by blade dicing for final separation. This sequencing ensures that the thin beam breaking occurs during the controlled blade dicing stage rather than during plasma etching, minimizing fragment generation and protecting chip surfaces while maintaining wafer-level processing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the manufacturing of semiconductor chips with complex shapes, enhancing productivity and reducing laser scattering, thereby improving yield and adaptability for ion trap devices.
Implementation Method 1
performing a plasma dicing process based on a predetermined shape of an outline of each of a plurality of semiconductor chips
Implementation Method 2
performing a blade dicing process such that a remaining portion of the outline of the semiconductor chip including a connection area between adjacent ones of the semiconductor chips is cut along a straight line
Data Source
AI summary
A method of manufacturing a semiconductor chip at a wafer level is disclosed. The method includes performing a plasma dicing process based on a predetermined shape of an outline of each of a plurality of semiconductor chips such that a dicing line along a portion of the outline extends throughout a wafer, and performing a blade dicing process such that a remaining portion of the outline of the semiconductor chip including a connection area between adjacent ones of the semiconductor chips is cut along a straight line.