Wafer Chip Security via Secret Key Memory Integration
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Solution Overview
Problem
Existing methods for fabricating integrated circuits are costly, complex, and lack security, particularly in wafer testing and chip identification, as they require toxic ink, separate file management, and risk data loss or misassociation.
Innovation Solution
A process involving writing secret keys into memories on the wafer for chip locking and unlocking, using contactless communication via scribe lines, allowing for secure and automatic testing and separation of defective chips without external files or ink, with a processing chip facilitating communication and data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ink is used to mark defective chips for identification, then defective chips can be visually identified during dicing, but the process becomes expensive, complex, and requires special machines and toxic material management
Solution Approach 1:
The patent extracts the identification information from external marking systems and stores it directly within the chip's memory structure. Test results and chip identifiers are written into memory cells that are part of the chip itself, eliminating the need for external ink marking systems, special deposition machines, and ink management infrastructure.
Solution Approach 2:
The patent introduces memory cells as an intermediary between the testing process and the identification process. Instead of directly marking chips with ink, the test results are stored in memory cells which then serve as the identification mechanism during dicing, simplifying the overall system while maintaining identification capability.
2Loss of information
If test data is stored in an independent external file, then chip identification information can be stored and transmitted, but the process requires separate file management, transmission between entities, and carries risks of data loss or misassociation
Solution Approach 1:
The patent merges the test data storage function with the chip structure itself by writing test results directly into memory cells on the wafer. This eliminates the need for separate external files and their associated management, transmission, and security concerns, while ensuring the data remains permanently associated with the correct chip.
Solution Approach 2:
The wafer structure itself provides the storage service for test data through its integrated memory cells. Instead of requiring external file systems and management infrastructure, the chip structure autonomously stores and preserves its own test results, eliminating the need for separate data management processes between fabrication entities.
3Measurement precision
If ink marking is used for chip identification, then defective chips can be sorted during dicing, but the process requires toxic material handling and special safety precautions for personnel and environment
Solution Approach 1:
The patent converts the potentially harmful ink marking process into a beneficial electronic storage process. Instead of using toxic materials that require safety precautions, the solution uses non-toxic electronic memory cells to store identification information, eliminating harmful factors while maintaining the ability to detect and sort defective chips.
4Adaptability or versatility
If separate entities handle wafer fabrication and integrated circuit assembly, then specialized functions can be divided, but the process requires complex data transmission and file management between entities
Solution Approach 1:
The patent merges the data storage function into the physical chip structure itself, so that when wafers are transferred between fabrication entities, the identification and test data travel with the chips rather than requiring separate file transmission systems. This maintains the benefits of specialized entity functions while eliminating complex data management overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a cost-effective, secure, and efficient method for fabricating integrated circuits by enabling secure chip identification and testing directly on the wafer, reducing the risk of data loss and misassociation, and simplifying the dicing process.
Implementation Method 1
The contactless communication may be of an inductive or a capacitive type.
Implementation Method 2
The contactless communication may be of an inductive or a capacitive type.
Data Source
AI summary
A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing the secret key into at least one memory present on the wafer.