Wafer-to-Chip Stacking with Gap Filling for Faster 3D Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The packaging of integrated circuits involves lengthy process cycles, low throughput, and high costs due to the need for multiple pick-and-place processes to stack individual chips, which is inefficient and costly.
Innovation Solution
The method involves bonding wafers to chips or other wafers, using gap-filling materials to fill gaps between chips, and employing direct wafer bonding or hybrid bonding techniques to improve throughput and reduce manufacturing costs by using wafers instead of individual chips, thereby simplifying the stacking process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple individual chips are stacked using pick-and-place processes, then the packaging can be completed, but the process cycle time becomes long and throughput becomes low
Solution Approach 1:
The patent merges multiple individual chip stacking operations into a single wafer-level bonding operation. By bonding entire wafers containing multiple chips simultaneously, the process eliminates the need for repeated pick-and-place cycles, thereby dramatically reducing process cycle time and increasing packaging throughput.
Solution Approach 2:
The patent performs preliminary actions by pre-organizing multiple chips on a wafer in their final stacked positions before bonding. This pre-arrangement allows all chips to be placed and bonded in one operation rather than sequentially, eliminating waiting time between placement operations and reducing overall process cycle time.
2Ease of manufacture
If multiple pick-and-place processes are used to stack chips, then the packaging can be completed, but the manufacturing cost becomes high
Solution Approach 1:
The patent combines multiple sequential pick-and-place operations into a single wafer-level bonding step. This consolidation reduces the number of process equipment uses, decreases process complexity, and lowers manufacturing costs while simultaneously maintaining high packaging throughput through parallel processing of multiple chips.
3Device complexity
If individual chips are used for stacking, then the packaging can be completed, but the process complexity increases
Solution Approach 1:
The patent merges multiple discrete chip handling operations into a single integrated wafer-level bonding process. This reduces process complexity by eliminating intermediate steps such as individual chip picking, positioning, and placement, while achieving high throughput through the parallel processing capability of wafer-level operations.
4Productivity
If wafers are used instead of individual chips, then the throughput is improved and cost is reduced, but the gaps between chips need to be filled
Solution Approach 1:
The patent performs gap-filling as a preliminary action immediately after wafer bonding. By filling gaps between chips on the wafer before subsequent processing steps, the method simplifies the overall process flow and avoids the need for additional gap-filling operations at later stages, thereby reducing process complexity while maintaining high throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances packaging throughput and reduces manufacturing costs by eliminating the need for individual chip placement and improves yield by using mature technology for wafers while utilizing advanced technology for discrete chips.
Implementation Method 1
bonding a first wafer to a first carrier... bonding a second wafer to a first wafer
Data Source
AI summary
In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.