Wafer-Level Chip Stacking with Through-Vias for Higher Packaging Throughput
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Solution Overview
Problem
The packaging of integrated circuits involves lengthy process cycles, low throughput, and high costs due to the need for multiple pick-and-place processes to stack individual chips, which is inefficient and costly.
Innovation Solution
The method involves bonding wafers instead of individual chips, using direct wafer bonding and hybrid bonding techniques to stack chips, reducing the need for individual chip placement and improving throughput by using wafers with pre-formed through-vias and gap-filling processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If individual chips are picked and placed one by one to stack multiple levels, then precise chip placement is achieved, but the process cycle time becomes very long and throughput is low
Solution Approach 1:
Multiple individual chip placement operations are merged into a single wafer-level bonding operation. The patent bonds entire wafers containing multiple chips simultaneously, eliminating the need for sequential pick-and-place of individual chips, thus dramatically increasing throughput while maintaining placement precision through wafer-level alignment techniques.
Solution Approach 2:
Chips are pre-arranged in their final stacked configuration on the wafer before bonding. The wafer-level approach allows all chips to be positioned and prepared in advance, and then bonded as a unit, rather than placing chips individually during the packaging process, which reduces overall process cycle time.
2Manufacturing precision
If multiple pick-and-place processes are used to stack chips at different levels, then individual chip placement is precise, but the manufacturing cost increases
Solution Approach 1:
Multiple sequential pick-and-place operations are combined into a single wafer bonding step. This consolidation reduces the number of process steps, equipment requirements, and labor involved, thereby lowering manufacturing costs while maintaining precise chip placement through wafer-level alignment and bonding techniques.
Solution Approach 2:
The patent uses wafer-level replication where identical chip arrangements are created across the entire wafer surface. This allows for high-volume production of uniformly stacked chip packages at lower per-unit costs compared to individual chip handling, while maintaining precise placement through the replicated wafer pattern.
3Shape
If gap-filling and planarization processes are performed after each chip placement, then flat packaging surface is achieved, but the process complexity and time increase
Solution Approach 1:
Gap-filling and planarization operations that would traditionally be performed after each individual chip placement are merged into single post-bonding processes. After the entire wafer is bonded in one step, gap-filling and planarization are performed once for the complete structure, significantly reducing process complexity and cycle time while achieving the required surface flatness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces manufacturing time and costs by improving the efficiency of chip stacking and gap-filling processes, allowing for higher yield and more cost-effective production of stacked chip packages.
Implementation Method 1
bonding wafers instead of individual chips, using direct wafer bonding and hybrid bonding techniques to stack chips
Implementation Method 2
bonding wafers instead of individual chips, using direct wafer bonding and hybrid bonding techniques to stack chips
Data Source
AI summary
In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.