Wafer-Scale Chiplet Redundancy With Mesh Interconnect Rerouting
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Solution Overview
Problem
Wafer-scale integration (WSI) faces challenges such as low yield, low defect tolerance, and high interconnect complexity, particularly in chiplet-based approaches where bonding failures and increased wire lengths lead to reduced yield and software compilation issues.
Innovation Solution
Implementing a hierarchical network topology with fully-connected, fat-tree, or torus configurations for chiplet redundancy, utilizing interposer substrates with active network elements to maintain logical topology and reroute data through alternative paths in case of failures, ensuring efficient redundancy and fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chiplet-based wafer-scale integration is implemented, then performance and density are improved, but yield and defect tolerance deteriorate
Solution Approach 1:
The system is divided into multiple independent chiplet groups organized in a hierarchical network topology. Each group contains multiple chiplets that can be independently managed, allowing failed chiplets to be isolated and replaced without affecting the entire wafer-scale system, thereby improving yield and defect tolerance while maintaining high performance and density.
Solution Approach 2:
The patent implements dynamic reconfiguration capabilities that allow the system to change its operational parameters by rerouting data paths and activating backup chiplets when failures occur. This parameter change capability enables the system to maintain functionality despite defects, improving reliability without sacrificing the performance benefits of chiplet-based integration.
2Reliability
If hierarchical network topology with redundancy is implemented, then fault tolerance is improved, but interconnect complexity increases
Solution Approach 1:
The interconnect network is segmented into hierarchical levels with standardized interfaces at each level. This segmentation reduces overall complexity by breaking down the complex routing problem into smaller, manageable segments that can be independently controlled and managed, while still providing redundant paths for fault tolerance.
Solution Approach 2:
The patent introduces intermediary components such as switches and routers at hierarchical levels that mediate between chiplets and the rest of the network. These intermediaries simplify the interconnect complexity by providing standardized interfaces and automated routing logic, reducing the burden on individual chiplets while maintaining fault tolerance through redundant paths.
3Reliability
If redundant paths are provided for fault tolerance, then reliability is improved, but overhead and latency increase
Solution Approach 1:
The system performs preliminary actions by pre-establishing redundant paths and performing health checks on chiplets before failures occur. When a failure is detected, the system can quickly activate pre-configured backup paths without requiring complex real-time routing decisions, thereby maintaining high reliability while minimizing the time overhead associated with fault recovery.
Solution Approach 2:
The patent implements dynamic path selection capabilities that allow the system to adaptively choose the most efficient data paths based on current system conditions. This dynamics enables the system to use direct paths when available (minimizing latency) while automatically switching to redundant paths when failures occur (maintaining reliability), thus optimizing the trade-off between overhead and reliability.
Data Source
AI summary
A wafer-level assembly of chiplets comprising a plurality of groups of chiplets including a first group of chiplets and a second group of chiplets, wherein the first group of chiplets is organized as a first fully-connected configuration, wherein the second group of chiplets is organized as a second fully-connected configuration. The wafer-level assembly of chiplets further comprises a plurality of interconnects including a first interconnect and a second interconnect, wherein the first interconnect couples a first chiplet of the first group of chiplets with a first chiplet of the second group of chiplets, wherein the second interconnect couples a second chiplet of the first group of chiplets with a second chiplet of the second group of chiplets, and wherein the plurality of interconnects is arranged in a mesh configuration.