Wafer Chuck Cooling Plate with Multi-Layer Coolant Channels

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Solution Overview

Problem

Existing wafer placement apparatuses with single-layer coolant channels suffer from temperature non-uniformity and inefficient cooling due to inferior thermal conductivity and temperature drop characteristics, particularly when using a sheath electrode with lower thermal conductivity.

Innovation Solution

A wafer placement apparatus featuring a ceramic plate with embedded electrostatic and heater electrodes and a cooling plate with a multi-layer coolant channel structure, where layers are stacked vertically and spaced differently from the wafer placement surface, allowing for independent temperature adjustment and enhanced cooling efficiency without a sheath electrode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-layer coolant channel is used, then the device complexity is reduced, but the temperature uniformity and cooling efficiency deteriorate

Engineering Contradiction:
Improvecoolant channel structureVSAvoidtemperature uniformity
Core Design Contradiction:
Device complexityVSTemperature

Solution Approach 1:

The patent transitions from a single-layer coolant channel to a multi-layer coolant channel structure, adding the vertical dimension to the channel layout. This allows coolant channels to be distributed at different heights within the cooling plate, improving temperature uniformity and cooling efficiency without excessive complexity increase.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The coolant channel system is segmented into multiple layers, with each layer serving specific cooling zones. The first coolant channel is positioned closer to the wafer placement surface while the second coolant channel is positioned farther away, allowing independent temperature control of different regions.

Inventive Principle:
Principle #1Segmentation

2Temperature

If a sheath electrode is used in the cooling plate, then the electrostatic chuck can be heated, but the cooling efficiency deteriorates due to inferior thermal conductivity

Engineering Contradiction:
Improvetemperature control capabilityVSAvoidcooling efficiency
Core Design Contradiction:
TemperatureVSLoss of energy

Solution Approach 1:

The patent removes the sheath electrode from the cooling plate structure, eliminating the component with inferior thermal conductivity that hindered cooling efficiency. Temperature control is achieved through the multi-layer coolant channel system alone, which provides superior thermal management.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the electrode-based heating system with a coolant-based thermal management system. Instead of using electrical resistance heating through sheath electrodes, the system uses circulated coolant through multi-layer channels to achieve both heating and cooling functions more efficiently.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If the coolant channel is positioned closer to the wafer placement surface, then the cooling efficiency is improved, but the temperature uniformity deteriorates due to insufficient cooling in other regions

Engineering Contradiction:
Improvecooling efficiencyVSAvoidtemperature uniformity
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent addresses the positioning dilemma by creating a multi-layer coolant channel structure where channels are distributed at different vertical positions. This allows the system to simultaneously achieve efficient cooling near the wafer surface and uniform temperature distribution throughout the entire electrostatic chuck volume.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The multi-layer coolant channel structure improves temperature uniformity and cooling efficiency by compensating for insufficient cooling and fine-tuning temperature distribution across the wafer, ensuring consistent and effective heat management during processing.

Implementation Method 1

a cooling plate disposed on an undersurface of the ceramic plate opposite to the wafer placement surface to cool the ceramic plate

Methodology Applied
Scientific EffectHeat transfer: Conduction (thermal)

Implementation Method 2

a coolant channel, and the coolant channel has a multi-layer structure at least partially including two or more layers stacked vertically

Methodology Applied
Scientific EffectConvection: Convection

Implementation Method 3

a ceramic plate having a top surface including a wafer placement surface, the ceramic plate allowing at least one of an electrostatic electrode and a heater electrode to be embedded therein

Methodology Applied
Scientific EffectElectrostatic force: Electrostatics

Implementation Method 4

a ceramic plate allowing at least one of an electrostatic electrode and a heater electrode to be embedded therein

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS11784078B2Wafer placement apparatus
Publication Date: 2023.10.10 NGK INSULATORS LTD
  • US11784078B2 patent drawing
  • US11784078B2 patent drawing
  • US11784078B2 patent drawing

AI summary

A wafer placement apparatus includes a ceramic plate having a top surface including a wafer placement surface, the ceramic plate allowing at least one of an electrostatic electrode and a heater electrode to be embedded therein; and a cooling plate disposed on an undersurface of the ceramic plate opposite to the wafer placement surface to cool the ceramic plate, wherein the cooling plate includes a coolant channel, and the coolant channel has a multi-layer structure at least partially including two or more layers stacked vertically, the two or more layers being spaced different distances apart from the wafer placement surface.