Wafer Circuit Testing Architecture With Shared Pads And Switching
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Solution Overview
Problem
Existing architectures for testing integrated circuits on wafers face challenges due to leakage currents, parasitic effects, and difficulties in accurate measurement caused by shared pads between chips and Test Element Group (TEG) structures, as well as issues with hard materials on pads leading to chipping during singulation and increased costs from complex structures.
Innovation Solution
A testing architecture that includes switching circuitry coupled to pads shared by integrated circuits and TEG structures, with enable pads and fuse links, allowing for flexible and reliable testing while avoiding the use of hard materials in scribe lines, and reinforcing the seal ring with pillar structures to prevent chipping during singulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If shared pads are used between chips and TEG structures, then testing of both integrated circuits and TEG structures is enabled, but leakage currents and parasitic effects cause measurement inaccuracies
Solution Approach 1:
The patent divides the testing function by separating TEG structure testing from chip testing through dedicated pads. TEG structures have their own specific pads rather than sharing with chips, which segments the electrical paths and eliminates cross-interference between the two testing functions.
Solution Approach 2:
The patent introduces switching circuitry as an intermediary component that controls the connection between pads and TEG structures. This mediator enables selective activation of TEG testing only when needed, preventing parasitic effects from affecting chip measurements during normal operation.
2Strength
If hard materials are deposited on pads in scribe lines, then pad strength is increased, but chipping occurs during singulation
Solution Approach 1:
The patent extracts the problematic hard material deposition from the scribe line area by positioning TEG structures away from scribe lines. This removes the source of chipping issues while preserving the mechanical integrity needed for singulation.
Solution Approach 2:
The patent applies different material properties to different locations: hard materials are deposited only on pads located in active chip areas where strength is needed, while scribe line regions maintain their original mechanical properties suitable for clean separation during singulation.
3Reliability
If complex structures with multiple metal layers are used for TEG pads, then electrical connectivity is improved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent employs switches that can dynamically connect or disconnect TEG structures from their pads based on testing requirements. This dynamic control simplifies the overall structure by using standard switching components rather than permanently complex multi-layer configurations, reducing manufacturing complexity while maintaining reliable electrical connectivity when needed.
Data Source
AI summary
A testing architecture for integrated circuits on a wafer includes at least one first circuit of a structure test element group (TEG) realized in a scribe line providing separation between first and second integrated circuits. At least one pad is shared by a second circuit inside at least one of the first and second integrated circuits and the first circuit. Switching circuitry is coupled to the at least one pad and to the first and second circuits.