Wafer Composite Spacer Disk Bonding for Thin Semiconductor Chips
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to enhance productivity and yield while reducing parasitic effects and material usage in thinner silicon devices, particularly in SOI technology, where conventional methods struggle to efficiently fabricate thin semiconductor layers with minimal crystalline material.
Innovation Solution
A method involving the formation of a layer stack with a device layer and an insulator layer, where a spacer disk is adhesive-bonded to the layer stack, allowing the wafer composite to be divided into individual semiconductor chips, ensuring compatibility with conventional tools for assembly, test, and packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional methods are used to fabricate thin semiconductor layers, then parasitic effects are reduced, but manufacturing complexity increases and productivity decreases
Solution Approach 1:
The invention divides the semiconductor manufacturing process into separate stages: first forming the thin active semiconductor layer with insulator layers on a first substrate, then bonding this layer stack to a second substrate. This segmentation allows the thin layer fabrication to be optimized for low parasitic effects while the bonding process enables high-volume production, resolving the contradiction between reducing parasitic effects and maintaining productivity
Solution Approach 2:
The invention introduces a second substrate as an intermediary carrier that receives the pre-fabricated thin active semiconductor layer. This intermediary allows the thin layer to be manufactured with precision (reducing parasitic effects) while the second substrate provides a platform for efficient handling and mass production (improving productivity)
2Object-affected harmful factors
If thinner semiconductor layers are used, then parasitic capacitances are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process is segmented into two independent stages: precise thin layer formation on a first substrate, and subsequent bonding to a second substrate. This allows the thin layer fabrication to focus solely on achieving precise thickness control (reducing parasitic capacitances) without the added complexity of simultaneous handling and bonding, thereby managing manufacturing precision requirements effectively
Solution Approach 2:
The active semiconductor layer and insulator layers are preliminarily formed and precisely controlled on the first substrate before bonding to the second substrate. This preliminary action allows for optimized thickness precision in the critical thin layers while the second substrate is added later to provide mechanical support and enable mass production
3Reliability
If more crystalline semiconductor material is grown, then device performance improves, but material cost increases
Solution Approach 1:
The invention extracts only the essential thin active semiconductor layer containing the electronic elements from the bulk substrate, bonding it to a second substrate. This extraction eliminates the need to grow thick crystalline semiconductor material, reducing material costs while maintaining device performance through the preserved thin active layer with optimized parasitic characteristics
Solution Approach 2:
The first substrate serves as a temporary, disposable platform for growing the thin active semiconductor layer and insulator layers with high precision. After the thin layer is formed and bonded to the second substrate, the first substrate can be discarded. This approach allows high-performance thin layer fabrication without the cost of maintaining large volumes of crystalline material
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of thin semiconductor chips with adjusted thickness, ensuring compatibility with existing equipment and processes, thereby improving productivity and yield while reducing material usage.
Implementation Method 1
A spacer disk is adhesive bonded on the layer stack on a side opposite the device layer
Data Source
Figure 1A~1C
Figure 2A~2B
Figure 2C~2D
AI summary
A layer stack (130) is formed that includes a device layer (110) and an insulator layer (120). The device layer (110) includes electronic elements (315). The insulator layer (120) is adjacent to a back surface (112) of the device layer (110). A spacer disk (190) is adhesive bonded on the layer stack (130) on a side opposite the device layer (110). The spacer disk (190) and the layer stack (130) form a wafer composite (100). The wafer composite (100) is divided into a plurality of individual semiconductor chips (900), wherein each semiconductor chip (900) includes a portion of the layer stack (130) and a portion of the spacer disk (190).