Wafer Contact Annealing for Low-Damage Electrical Testing
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Solution Overview
Problem
Conventional wafer testing methods cause significant heat treatment, leading to degradation of semiconductor properties and making only a small percentage of tested wafers suitable for further processing, as they require additional thermal annealing, which affects electrical and optical properties.
Innovation Solution
A method involving local annealing of the semiconductor layer sequence using radiation, specifically heating the contact elements to establish low-resistance electrical contacts without heating the entire wafer, allowing up to 99% of tested wafers to be used for further processing without property alteration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer testing methods are used with full wafer heat treatment, then electrical contact is established between contact elements and semiconductor layer sequence, but semiconductor properties are degraded and only small percentage of wafers are suitable for further processing
Solution Approach 1:
The patent applies local annealing only to the specific regions where contact elements are positioned, rather than heating the entire wafer. This localized thermal treatment establishes electrical contact at the contact points while leaving the rest of the semiconductor layer sequence unaffected, thus maintaining semiconductor properties in the non-contact regions and enabling further processing of up to 99% of tested wafers.
2Reliability
If full wafer annealing is performed during testing, then electrical contact is established, but additional thermal treatment alters electrical and optical properties requiring re-annealing
Solution Approach 1:
By confining the annealing process to only those regions where contact elements are located, the patent eliminates the need for subsequent full-wafer re-annealing. The localized thermal treatment establishes electrical contact without altering the electrical and optical properties of the bulk semiconductor material, thereby eliminating time loss from additional thermal processing steps.
3Productivity
If conventional testing with extensive heat treatment is applied, then functionality is tested, but wafer is significantly impaired reducing further processing capability
Solution Approach 1:
The patent enables efficient functionality testing through localized annealing that establishes electrical contact only where needed. This approach maintains the semiconductor properties of the wafer in regions outside the contact zones, preserving the wafer's suitability for further processing and achieving high productivity without significant wafer impairment.
Solution Approach 2:
The patent applies partial annealing action only to the extent necessary for establishing electrical contact at contact element locations, rather than applying excessive full-wafer heat treatment. This partial action achieves the required testing functionality while minimizing thermal exposure and preserving wafer quality for subsequent manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes wafer impairment during testing, enabling efficient functionality testing while maintaining the quality of semiconductor chips by avoiding double heat treatment, thus preserving the electrical and optical properties of the wafers.
Implementation Method 1
the semiconductor layer sequence is configured for generating electromagnetic radiation
Implementation Method 2
heating the contact elements to establish low-resistance electrical contacts without heating the entire wafer
Data Source
AI summary
In an embodiment a method includes providing a wafer with a semiconductor layer sequence arranged on a substrate, attaching at least one first contact element to a main surface of the semiconductor layer sequence facing away from the substrate, attaching at least one second contact element to the main surface of the semiconductor layer sequence at a distance to the first contact element and applying a first electrical potential to the first contact element and a second electrical potential to a second contact element, wherein the first electrical potential and the second electrical potential are different from each other, wherein, by locally annealing the semiconductor layer sequence, a first contact region is formed in a region of the first contact element and a second contact region, which is spaced apart from the first contact region, is formed in a region of the second contact element.