Wafer Conveyance via Load Lock Positioning and Dual-Arm Transfer
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Solution Overview
Problem
Existing wafer processing apparatuses face challenges in rapidly and accurately conveying wafers to predetermined positions on processing stages due to the need for individual wafer adjustments, which slows down the process and causes vibration in robot arms, affecting throughput and uniformity.
Innovation Solution
A wafer processing apparatus featuring a first robot, a load lock apparatus with two stages, and a second robot that simultaneously conveys two wafers between load lock stages and processing stages, with a controller adjusting the wafer positions to account for positional shifts, enabling rapid and accurate placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wafer positions are adjusted one wafer at a time using the robot arm, then accurate placement on processing stages is achieved, but conveyance speed decreases and throughput is reduced
Solution Approach 1:
The robot arm performs preliminary positioning of wafers on the load lock stages before the conveyance operation. By pre-positioning wafers at their destination locations (accounting for positional shifts) on the load lock stages, the system eliminates the need for time-consuming alignment operations during the conveyance cycle, thereby resolving the contradiction between accuracy and speed
Solution Approach 2:
The system combines multiple wafer conveyance operations into a single simultaneous motion of the robot arm. By carrying and placing multiple wafers in one conveyance action, the system achieves both rapid conveyance and accurate placement, resolving the contradiction between throughput and precision
2Manufacturing precision
If the robot arm is extended to adjust wafer positions, then wafer alignment is achieved, but vibration occurs and stability decreases
Solution Approach 1:
Wafer positioning is performed as a preliminary action before conveyance, when the robot arm is in a stable, retracted position. By completing alignment operations before extension, the system avoids vibration-induced positioning errors that would occur if alignment were attempted during the extended conveyance state
Solution Approach 2:
The wafer placement process is segmented into two distinct phases: (1) positioning phase where wafers are placed on load lock stages with precise positioning, and (2) conveyance phase where pre-positioned wafers are transferred to processing stages. This segmentation allows each phase to optimize for its specific requirement (precision or speed) without compromising the other
3Manufacturing precision
If individual wafer centering is performed, then accurate placement is achieved, but processing time increases
Solution Approach 1:
Wafer centering is performed as a preliminary action on the load lock stages before conveyance. By pre-centering wafers at their final destination positions, the system eliminates the need for time-consuming centering operations during the conveyance cycle, thereby resolving the contradiction between centering accuracy and processing time
Solution Approach 2:
The system uses the load lock stages as self-service positioning platforms where wafers are pre-positioned and pre-centered. This self-service approach allows wafers to be prepared for their final destinations without requiring active intervention or time-consuming operations during the main conveyance process
Data Source
AI summary
A wafer processing apparatus includes a controller connected to a first robot and a second robot. The controller controls the first robot so that the wafer is placed on a first load lock stage in such a way that the center of the wafer is shifted from the center of the first load lock stage by a first position shift amount and another wafer is placed on a second load lock stage in such a way that the center of the wafer is shifted from the center of the second load lock stage by a second position shift amount. The controller controls the second robot so that the second robot simultaneously conveys two wafers between the first and second load lock stages, and a first processing stage and a second processing stage.