Semiconductor Wafer Cryogenic Stress Relief for Warpage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in achieving a flat substrate surface during advanced lithography operations due to substrate warpage and deformation, which affects device reliability and manufacturing processes, and existing methods like process changes or hot embossing are not suitable for high-volume manufacturing or structures with metal-rich layers.

Innovation Solution

A cryogenic treatment process is applied to semiconductor wafers, involving cooling to a low temperature, holding at that temperature, and then heating back to room temperature to reduce internal stress and warpage by inducing plastic deformation, thereby alleviating thermal expansion mismatch-induced warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If process changes or hot embossing are used to reduce warpage, then substrate flatness is improved, but manufacturing complexity and suitability for high-volume production deteriorate

Engineering Contradiction:
Improvesubstrate flatnessVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies cryogenic treatment by changing the temperature parameter to extremely low values (cryogenic range) to induce controlled plastic deformation in the substrate. This thermal parameter change reduces internal stress and warpage without requiring complex mechanical embossing equipment or process modifications, thereby improving substrate flatness while maintaining manufacturing simplicity and suitability for high-volume production

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If cryogenic treatment is applied to reduce warpage, then substrate flatness and manufacturing reliability are improved, but energy consumption increases

Engineering Contradiction:
Improvesubstrate flatnessVSAvoidenergy consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The cryogenic treatment utilizes phase transition principles by cooling the substrate to cryogenic temperatures where material properties change, inducing plastic deformation that permanently reduces warpage. The brief exposure to extreme cold followed by rapid return to ambient temperature creates the desired structural change with minimal total energy input compared to sustained thermal or mechanical processes

Inventive Principle:
Principle #36Phase transitions

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The cryogenic treatment effectively reduces warpage and internal stress in semiconductor wafers, improving substrate flatness and manufacturing reliability, and can be applied before or after dicing and packaging processes, making it suitable for high-volume semiconductor manufacturing.

Implementation Method 1

A cryogenic treatment process is applied to semiconductor wafers, involving cooling to a low temperature, holding at that temperature, and then heating back to room temperature to reduce internal stress and warpage by inducing plastic deformation

Methodology Applied
Scientific EffectCryogenic treatment: Cryogenics

Implementation Method 2

heating back to room temperature to reduce internal stress and warpage by inducing plastic deformation

Methodology Applied
Scientific EffectThermal heating: Heating

Data Source

PatentUS20230378003A1Method of manufacturing semiconductor devices
Publication Date: 2023.11.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230378003A1 patent drawing
  • US20230378003A1 patent drawing
  • US20230378003A1 patent drawing

AI summary

In a method, a structure including two or more materials having different coefficients of thermal expansion is prepared, and the structure is subjected to a cryogenic treatment. In one or more of the foregoing and following embodiments, the structure includes a semiconductor wafer and one or more layers are formed on the semiconductor wafer.