Wafer Defect Inspection Alignment Correction Loop
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Solution Overview
Problem
Existing semiconductor wafer defect inspection systems face challenges in achieving accurate target-reference wafer image alignment due to localized heating, die size changes, and misalignment between die rows and columns, which degrades defect location identification accuracy.
Innovation Solution
A method involving pre-inspection alignment, execution of swaths to generate images, and real-time alignment using offsets to refine thermal scaling factors and rotational corrections, ensuring precise alignment during defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pre-inspection alignment and thermal scaling correction are performed, then alignment accuracy is improved, but inspection time is increased due to multiple alignment steps
Solution Approach 1:
The patent performs pre-inspection alignment including coarse and fine theta correction, thermal scaling factor calculation, and XY premap alignment before the main inspection process. This preliminary alignment work establishes accurate reference frames and correction factors that enable faster defect detection during the actual inspection, resolving the contradiction by preparing alignment data in advance.
Solution Approach 2:
The patent implements run-time alignment that uses feedback from the inspection process itself to continuously refine alignment parameters. By monitoring actual wafer positions and thermal changes during inspection, the system dynamically adjusts alignment corrections, maintaining high accuracy without requiring excessive pre-alignment time.
2Measurement precision
If run-time alignment is performed during inspection, then defect location accuracy is improved, but processing speed is reduced
Solution Approach 1:
The patent applies partial alignment corrections during run-time by focusing only on the specific alignment parameters that drift during inspection (such as thermal scaling and rotational theta), rather than performing complete realignment. This selective approach maintains accuracy for the critical parameters while minimizing processing overhead and maintaining inspection speed.
3Measurement precision
If multiple alignment steps including XY premap are executed, then image alignment precision is improved, but system complexity increases
Solution Approach 1:
The patent divides the alignment process into distinct segmented steps: pre-aligner (notch and center location), low-magnification alignment (coarse theta), high-magnification alignment (fine theta and thermal scaling), and XY premap. Each segment addresses specific alignment requirements with appropriate precision, making the complex overall process more manageable and systematic while achieving high cumulative accuracy.
Data Source
AI summary
A method of semiconductor-wafer image alignment is performed at a semiconductor-wafer defect-inspection system. In the method, a semiconductor wafer is loaded into the semiconductor-wafer defect-inspection system. Pre-inspection alignment is performed for the semiconductor wafer. After performing the pre-inspection alignment, a first swath is executed to generate a first image of a first region on the semiconductor wafer. An offset of a target structure in the first image with respect to a known point is determined. Defect identification is performed for the first image, using the offset. After executing the first swath and determining the offset, a second swath is executed to generate a second image of a second region on the semiconductor wafer. While executing the second swath, run-time alignment of the semiconductor wafer is performed using the offset.