Wafer Defect Binning via Design Alteration
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in efficiently removing nuisance defects from wafer inspection data, leading to increased computational resources and reduced productivity due to the inclusion of non-critical pattern groups in defect binning.
Innovation Solution
A computer-implemented method that identifies non-critical areas in a wafer design, generates an altered design by eliminating features in these areas, and uses the altered design to bin defects, ensuring that only critical features are considered for defect detection and grouping, thereby reducing nuisance defects and improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If design-based binning is used to group all patterns, then defect detection coverage is improved, but the number of defect groups increases substantially making it difficult to identify critical patterns
Solution Approach 1:
The patent segments the wafer design into critical and non-critical areas based on yield impact. By dividing the design space and applying different binning strategies to each segment, the system maintains comprehensive defect detection while reducing the number of meaningful defect groups. Non-critical patterns are excluded from binning, eliminating nuisance bins while preserving critical pattern analysis.
Solution Approach 2:
The patent extracts and removes non-critical patterns from the binning process. By identifying and excluding patterns that do not impact yield, the system eliminates nuisance defect groups while maintaining detection coverage for critical patterns. This extraction approach reduces the complexity of defect groups without sacrificing measurement precision for important features.
2Measurement precision
If all patterns are included in defect binning, then comprehensive defect detection is achieved, but computational resources are wasted on nuisance bins reducing productivity
Solution Approach 1:
The patent segments patterns into critical and non-critical categories based on their impact on yield. By applying binning only to critical patterns, the system maintains comprehensive defect detection for yield-sensitive features while eliminating computational waste on non-critical patterns. This segmentation improves productivity by reducing the number of bins that require manual review.
Solution Approach 2:
The patent extracts non-critical patterns from the binning process, removing them from computational analysis. This extraction eliminates wasted computational resources on nuisance bins while preserving comprehensive detection capabilities for critical patterns. The result is improved productivity without sacrificing detection comprehensiveness for yield-impactful defects.
3Measurement precision
If smaller care areas are defined to reduce nuisance defects, then defect binning accuracy improves, but recipe setup effort and complexity increase significantly
Solution Approach 1:
The patent performs preliminary classification of patterns into critical and non-critical categories before the binning process. By pre-identifying which patterns impact yield, the system automatically determines appropriate care areas without requiring manual recipe configuration. This preliminary action improves binning accuracy while reducing setup effort, as the system self-configures based on design analysis rather than manual intervention.
Solution Approach 2:
The patent enables the binning system to automatically identify and configure care areas based on yield impact analysis of the design. Rather than requiring manual recipe setup, the system self-determines which patterns are critical and configures binning parameters accordingly. This self-service approach improves binning accuracy while eliminating the complexity of manual recipe configuration.
Data Source
AI summary
Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.