Wafer Defect Binning via Design Attribute Alignment
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Solution Overview
Problem
As semiconductor manufacturing processes approach design rule limits, existing inspection systems are overwhelmed by nuisance defects, reducing sensitivity and increasing costs due to the difficulty in distinguishing yield-relevant defects from non-critical ones, leading to inefficient data processing and reduced throughput.
Innovation Solution
A method and system for wafer inspection that aligns image patches with design information, derives multiple layer design attributes, and uses a decision tree to separate defects into bins based on yield impact, enabling more accurate defect detection and binning through computer subsystems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If inspection sensitivity is increased to detect smaller defects, then defect detection capability is improved, but the number of nuisance defects detected increases dramatically
Solution Approach 1:
The patent segments the large set of detected defects into multiple bins based on their location and characteristics. By dividing defects into different categories (e.g., yield-critical, yield-relevant, nuisance), the system can process and analyze each segment separately, reducing the overall complexity and enabling focused attention on critical defects while systematically managing the volume of nuisance defects through automated classification.
2Reliability
If more defects are detected on wafers, then inspection thoroughness is improved, but data processing capacity is overloaded and throughput is reduced
Solution Approach 1:
The patent applies local quality by assigning different processing priorities and analysis depths to different defect bins. Yield-critical defects receive immediate and detailed attention, while nuisance defects are processed with simpler filtering rules. This differentiated approach ensures that computational resources are concentrated on defects that matter most, maintaining inspection thoroughness for critical defects while preserving overall system throughput.
Solution Approach 2:
The system performs partial action by not processing all detected defects with the same level of detail. Instead, it applies appropriate processing depth based on defect classification - full analysis for yield-critical defects, reduced analysis for yield-relevant defects, and simple filtering for nuisance defects. This selective processing maintains reliability for critical defects while significantly reducing the overall data processing burden.
3Area of moving object
If design rules are shrunk to increase device density, then device capacity is improved, but the population of yield-relevant defects grows dramatically
Solution Approach 1:
The patent introduces a new dimension for defect analysis by incorporating multiple layer design attributes beyond the traditional single-layer inspection. By examining defects in the context of three-dimensional device structures and multiple fabrication layers, the system can better distinguish yield-relevant defects from nuisance defects even at smaller dimensions. This multi-dimensional approach enables effective defect management as device density increases through design rule shrinkage.
Data Source
AI summary
Methods and systems for design based sampling and binning for yield critical defects are provided. One method includes aligning each image patch in each inspection image frame generated for a wafer by an optical subsystem of an inspection system to design information for the wafer. The method also includes deriving multiple layer design attributes at locations of defects detected in the image patches. In addition, the method includes building a decision tree with the multiple layer design attributes. The decision tree is used to separate the defects into bins with different yield impacts on a device being formed on the wafer. The method also includes binning the defects with the decision tree.