Wafer Defect Calibration Using Layout-Based Critical Area Analysis
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Solution Overview
Problem
In semiconductor manufacturing, the identification of real open or short circuit failure defects is challenging due to random and systematic defects caused by equipment precision deviations and process limitations, leading to low yield and increased costs, as existing defect analysis methods struggle with precision and accuracy, especially with shrinking geometry dimensions and complex design layouts.
Innovation Solution
A smart defect calibration system that uses integrated circuit design layout data and Critical Area Analysis to calibrate defect sizes and coordinates, generating a more precise Killer Defect Index by correcting coordinate and size deviations, thereby improving defect classification and sampling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If defect inspection is performed using conventional methods with SEM and optical microscopes, then defect images can be captured, but coordinate and size deviations occur between defect inspection data and actual defect data, reducing measurement precision
Solution Approach 1:
The patent introduces a calibration value as an intermediary element that mediates between defect inspection data and actual defect data. This calibration value, derived from the relationship between design layout data and defect inspection data, corrects coordinate and size deviations without requiring direct modification of the inspection tools themselves.
Solution Approach 2:
The patent applies parameter changes by adjusting the calibration value based on the specific relationship between design layout data and defect inspection data. This dynamic calibration approach allows the system to adapt to different defect types, inspection conditions, and tool variations, thereby maintaining measurement precision across diverse scenarios.
2Productivity
If a small number of defect images are selected for analysis due to limited throughput, then processing time is reduced, but the ability to identify real killer defects is compromised
Solution Approach 1:
The patent replaces manual or simple automated defect selection with an intelligent classification system that uses calibration values and design layout data to automatically identify killer defects. This substitution of mechanical selection with intelligent analysis maintains high throughput while significantly improving the reliability of killer defect identification.
Solution Approach 2:
The system implements feedback by using calibration values derived from the relationship between design layout data and defect inspection data to continuously improve defect classification accuracy. This feedback mechanism ensures that the system learns from past classifications and adapts to better identify killer defects over time.
3Ease of manufacture
If conventional defect analysis methods are used without calibration, then the process is simpler and faster, but the accuracy of Critical Area_analysis and killer defect identification deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating calibration values based on the relationship between design layout data and defect inspection data before actual defect analysis. This preliminary calibration step, though adding some complexity, enables significantly more accurate Critical Area_analysis and killer defect identification without requiring complex real-time calculations during defect analysis.
Data Source
AI summary
A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. This method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.