Wafer Defect Detection Using Layout-Aware Multi-Dimensional Clustering
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Solution Overview
Problem
Conventional electron beam inspection (EBI) systems face challenges in detecting weak-signal defects due to high nuisance rates and low throughput, which limits their ability to effectively differentiate defects from nuisances and requires multiple scans for different environments, potentially damaging wafers in the process.
Innovation Solution
An improved EBI detection model that labels scan data with attributes from circuit layout streaming data using multi-dimensional clustering, enhancing defect differentiation and identifying unknown defect types, while reducing damage risk and improving throughput by correlating scan data with layout features and applying individual image filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If lower thresholds are set to detect weak-signal defects, then defect detection sensitivity is improved, but nuisance rates dramatically increase
Solution Approach 1:
The patent transitions from one-dimensional grey level analysis to multi-dimensional feature space analysis by incorporating additional attributes (brightness, contrast, edge strength, area, circularity) beyond the traditional grey level difference. This dimensional expansion allows the system to distinguish weak-signal defects from nuisances more effectively, achieving both high sensitivity and low nuisance rates simultaneously.
Solution Approach 2:
The patent changes the detection parameters by using multiple brightness and contrast settings across different scan tests rather than relying solely on grey level difference thresholds. By varying these parameters and analyzing results across multiple dimensions, the system can detect weak-signal defects while maintaining reliability and reducing false positives.
2Adaptability or versatility
If multiple scan tests are performed with different brightness levels to detect defects in different environments, then defect detection coverage is improved, but throughput is reduced and wafer damage increases
Solution Approach 1:
The patent merges multiple scan tests with different brightness and contrast settings into a single integrated inspection process. By combining multiple detection dimensions (brightness, contrast, edge strength, area, circularity) and analyzing them together through clustering algorithms, the system achieves comprehensive defect coverage while performing only one scan per wafer, thereby maintaining high throughput and preventing wafer damage.
Solution Approach 2:
The patent creates a universal inspection approach that uses multiple feature dimensions and clustering algorithms to handle diverse defect types across different environments (isolated and dense logic) within a single scan. This multi-functional approach eliminates the need for separate specialized scan tests, improving both versatility and productivity.
3Measurement precision
If multiple scan tests are performed on the same wafer, then defect detection accuracy is improved, but wafer damage risk increases
Solution Approach 1:
The patent performs preliminary data preparation by collecting and organizing multiple types of feature data (brightness, contrast, edge strength, area, circularity) from a single scan before analysis. By preparing all necessary detection dimensions in advance from one scan, the system achieves high detection accuracy without requiring repeated scans that would increase wafer damage risk.
Solution Approach 2:
The patent introduces clustering algorithms as an intermediary that processes and analyzes the multi-dimensional feature data from a single scan. This intermediary computational step enables accurate defect differentiation without requiring physical repeated scans of the wafer, thereby maintaining accuracy while preventing damage.
Data Source
AI summary
A system configured to detect defects on a wafer is provided. The system includes an inspection subsystem configured to acquire scan data of a target region on the wafer. The target region comprises a plurality of circuit layout streaming data on the wafer and the defects in proximity to the circuit layout streaming data or in the circuit layout streaming data. A graphic design subsystem (GDS) is configured to store a map of circuit layout streaming data of the wafer. A software tool for designing electronic systems is configured to label the scan data with attributes from the map of circuit layout streaming data. A decision subsystem is configured to qualify the process based on a predetermined defect level from the labeled scan data by using a multi-dimension clustering method, wherein the predetermined defect level is an accumulated defect formed on the semiconductor wafer during processing.