Wafer Defect Localization via Design Coordinate Alignment
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Solution Overview
Problem
As semiconductor device dimensions shrink, detecting and correcting defects becomes increasingly challenging due to limitations in imaging resolution and the inability to accurately determine the position of defects relative to electrical design patterns, leading to inefficient process control and potential yield losses.
Innovation Solution
A method and system that utilize a broadband plasma image data acquisition subsystem and a Scanning Electron Microscope (SEM) review tool to identify and confirm defects by associating them with tool coordinates, aligning the SEM with design polygons, and exporting design coordinate files for pattern of interest definition, enabling precise defect localization and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If imaging resolution is increased to accurately identify defect positions, then measurement precision improves, but device complexity and cost increase
Solution Approach 1:
The patent introduces design file coordinates as an intermediary reference system that bridges the inspection image coordinate system and the actual defect position. By using the design file as a mediator, the system can accurately locate defects without requiring the inspection hardware to achieve extremely high resolution, thus resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent transitions from a single coordinate system (inspection image coordinates) to a two-dimensional coordinate mapping approach (inspection coordinates + design file coordinates). This dimensional expansion allows the system to accurately identify defect positions by combining information from both coordinate systems, avoiding the need for excessively complex high-resolution imaging hardware
2Measurement precision
If inspection sensitivity is increased to detect smaller defects, then measurement precision improves, but the number of nuisance defects increases
Solution Approach 1:
The patent applies local quality by focusing inspection efforts on specific areas of interest identified through design file correlation. Instead of treating all detected defects equally, the system prioritizes defects that are spatially correlated with design features, effectively filtering out nuisance defects while maintaining high sensitivity for relevant defects
Solution Approach 2:
The patent uses partial action by performing correlation analysis only on defects that fall within regions of interest defined by the design file. Rather than analyzing all detected defects uniformly, the system selectively processes those with potential significance, reducing the burden of nuisance defect analysis while maintaining detection sensitivity
3Manufacturing precision
If process control is expanded to address all detected defects, then manufacturing precision improves, but productivity decreases
Solution Approach 1:
The patent implements local quality in process control by directing corrective actions only to defects that are spatially correlated with design features. This selective approach ensures that manufacturing precision is maintained for critical defects while avoiding unnecessary corrections for nuisance defects, thereby preserving productivity
Solution Approach 2:
The patent applies partial action by implementing process control measures only for the subset of defects identified as yield-relevant through correlation analysis. Rather than uniformly processing all detected defects, the system focuses resources on correcting only those defects that are likely to impact manufacturing quality, improving overall process control efficiency
4Measurement precision
If coordinate alignment between inspection and design is improved, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent uses the design file as an intermediary that provides a common reference framework for both inspection and manufacturing processes. By establishing coordinate transformations through the design file rather than through complex direct hardware alignment, the system achieves high coordinate alignment accuracy while minimizing device complexity
Solution Approach 2:
The patent creates a digital copy of the design coordinate system and uses it for correlation analysis. This virtual copying approach allows for precise coordinate alignment without requiring physical hardware modifications or complex alignment mechanisms, thus achieving measurement precision while keeping device complexity low
Data Source
AI summary
Systems and methods for automatic correction of drift between inspection and design for massive pattern searching are disclosed herein. Defects are identified in a scan of a wafer. The defects are associated with tool coordinates. An SEM review tool captures centered images of the defects. The SEM review tool is aligned with the wafer using design polygons in an imported design file. Design coordinates are exported and used to define patterns of interest and identifying locations of those patterns of interest.