Wafer Defect Prediction Using Distance-Based Abnormality Index
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Solution Overview
Problem
Conventional wafer defect detection methods using deep learning face challenges in securing prediction models for large-scale data and lack sufficient data explanation functions, while also consuming excessive simulation time.
Innovation Solution
A wafer defect test apparatus and system that includes a wafer variable generator, an abnormal wafer index generating circuit, and a prediction model generating circuit, which improves defect prediction performance and shortens simulation time by generating process variables, calculating Euclidean and Cosine distances, and creating abnormal wafer indexes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep learning methods are used for wafer defect detection, then prediction capability is improved, but simulation time increases excessively
Solution Approach 1:
The patent segments the defect detection process into multiple components: normal wafer determination unit, vector generation unit, distance calculation unit (Euclidean and Cosine), and defect prediction unit. This segmentation allows parallel processing and optimization of each component, reducing overall simulation time while maintaining prediction accuracy.
Solution Approach 2:
The patent transforms process data into vector representations and applies multiple distance metrics (Euclidean and Cosine) to characterize wafer similarities. By changing the parameter representation from raw process data to normalized vectors with multiple distance measures, the system achieves faster computation while improving prediction reliability.
2Reliability
If deep learning models are trained on large-scale data, then prediction accuracy is improved, but it becomes difficult to secure and process the data
Solution Approach 1:
The patent applies local quality by determining normal wafers individually based on their specific process characteristics and comparing them against reference wafers. Each wafer is evaluated with customized vector representations and distance metrics tailored to its process conditions, allowing accurate predictions without requiring uniform processing of all large-scale data.
Solution Approach 2:
The patent introduces vector representations as an intermediary between raw process data and defect predictions. The vector generation unit transforms complex process data into standardized vector formats, and distance calculation units compute similarities through these vectors, simplifying data processing while maintaining prediction accuracy.
3Loss of information
If explainable AI models are used, then data explanation function is improved, but simulation time is consumed excessively
Solution Approach 1:
The patent replaces complex explainable AI mechanisms with straightforward mathematical operations: vector generation, Euclidean distance calculation, Cosine distance calculation, and threshold-based defect determination. This substitution provides clear, interpretable results through deterministic mathematical relationships rather than complex AI reasoning, maintaining explainability while dramatically reducing computation time.
Data Source
AI summary
A wafer defect test apparatus in which a defect prediction performance is improved and a simulation time is shortened is provided. The wafer defect test apparatus comprises a wafer variable generator which receives a first structural measurement data and a first process condition data of a first wafer, and a second structural measurement data and a second process condition data of a second wafer, generates a first process variable and a second process variable based on the first structural measurement data and the first process condition data, and generates a third process variable and a fourth process variable based on the second structural measurement data and the second process condition data, an abnormal wafer index generating circuit which generates a first wafer vector of the first process variable and second process variable, generates a second wafer vector of the third process variable and fourth process variable, calculates a first Euclidean distance between the first wafer vector and the second wafer vector, calculates a first Cosine distance between the first wafer vector and the second wafer vector, and generates a first abnormal wafer index of the first wafer based on a product of the first Euclidean distance and the first Cosine distance, and a prediction model generating circuit which receives a first characteristic variable which is a test result of the first wafer, and generates a wafer defect prediction model through a regression based on the first process variable, the second process variable, the first characteristic variable, and the first abnormal wafer index.