Wafer Defect Analysis Using Electrical Netlist Overlay
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in accurately detecting and distinguishing between critical and nuisance defects on wafers, particularly as design rules shrink, leading to increased complexity in identifying defects that affect electrical parameters and yield, due to limitations in inspection system accuracy and sensitivity.
Innovation Solution
The use of electrical information, such as critical path data, to perform defect-related functions, including identifying critical defects, determining yield impact, and separating defects based on their electrical relevance, enables more precise defect analysis and process control by aligning inspection data with electrical design information in real-time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If inspection sensitivity is increased to detect smaller defects, then defect detection capability is improved, but the number of false positives and nuisance defects increases
Solution Approach 1:
The patent segments defects into two categories: critical defects that affect electrical parameters and nuisance defects that do not. This segmentation is achieved by overlaying inspection data with electrical design information (netlist, layout) to determine whether detected defects are located in electrically critical areas. This resolves the contradiction by allowing high inspection sensitivity while filtering out nuisance defects through electrical relevance analysis.
2Reliability
If comprehensive defect inspection is performed on the entire wafer, then defect detection coverage is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent applies local quality by directing full inspection resources only to electrically critical areas identified through overlay analysis with netlist and layout data. Non-critical areas receive reduced or no inspection. This resolves the contradiction by concentrating inspection efforts where they are most needed (electrically sensitive regions) while reducing or eliminating inspection in non-critical regions, thereby maintaining reliability for critical defects while improving throughput.
3Measurement precision
If all detected defects are reviewed and analyzed, then yield impact assessment is improved, but processing time and complexity increase
Solution Approach 1:
The patent extracts and separates critical defects from nuisance defects by using electrical design information (netlist, layout, critical path data) to filter the defect list. Only defects that are electrically relevant (located in critical areas, affecting signal paths, or impacting electrical parameters) are retained for detailed analysis. This resolves the contradiction by removing irrelevant defects from the analysis set, thereby maintaining accurate yield impact assessment while significantly reducing processing complexity.
Data Source
AI summary
Various methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions are provided. One computer-implemented method includes using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions. The one or more defect-related functions include one or more post-mask, defect-related functions.