Wafer Defect Tracing by Correlating Fail Bits and Defect Areas
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Solution Overview
Problem
During wafer manufacturing, defects often occur due to suspended particles in the air or inadequate cleaning, leading to Fail Bits (FBs) that reduce wafer yield, as existing methods fail to effectively trace and address the root cause of these defects.
Innovation Solution
A wafer defect tracing method and apparatus that involves obtaining defect data, determining the position and count of FBs, calculating the defect area and FB count, processing these data to obtain a correlation coefficient, and identifying the abnormal reason for FBs, thereby determining the cause of defects and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional defect detection methods are used, then defect detection is performed, but the root cause of defects cannot be effectively traced
Solution Approach 1:
The patent segments the wafer into multiple storage blocks and further divides each storage block into sub-regions. By analyzing defect distributions at these granular levels and correlating with FB positions, the method traces defects to specific manufacturing process segments, thereby identifying root causes that traditional whole-wafer analysis cannot detect.
Solution Approach 2:
The patent establishes a feedback loop by correlating defect data with FB position data, calculating correlation coefficients, and using this information to identify abnormal reasons. This feedback mechanism enables continuous improvement of defect analysis precision by learning from actual defect-FB relationships observed in manufacturing data.
2Measurement precision
If comprehensive defect analysis is performed on the entire wafer, then all defects are detected, but the analysis becomes complex and time-consuming
Solution Approach 1:
The patent divides the wafer into multiple storage blocks and further segments each block into sub-regions. This hierarchical segmentation reduces the complexity of analyzing the entire wafer by allowing focused analysis on specific segments, while still maintaining comprehensive defect detection through systematic coverage of all segments.
Solution Approach 2:
The patent applies local quality analysis by examining defect distributions and FB positions at the storage block and sub-region levels rather than treating the entire wafer uniformly. This localized approach reduces analytical complexity by focusing computational resources on specific areas with abnormal defect-FB correlations.
3Device complexity
If limited backup circuits are used, then circuit complexity is reduced, but the ability to repair FBs is insufficient
Solution Approach 1:
The patent performs preliminary analysis of defect-FB correlations before final chip qualification. By identifying storage blocks with abnormal correlation coefficients between defects and FB positions, the system can proactively determine which chips are likely to have repairable FBs, allowing limited backup circuits to be strategically allocated to chips that most need them.
4Productivity
If rapid defect identification is achieved, then yield improvement is enabled, but detailed defect analysis may be compromised
Solution Approach 1:
The patent enables rapid defect identification by segmenting the wafer into storage blocks and calculating correlation coefficients at this coarser level first. This hierarchical approach provides quick screening of abnormal areas, then allows detailed analysis to be focused only on specific sub-regions of interest, thereby maintaining analytical detail while improving overall speed.
Data Source
AI summary
Provided are a wafer defect tracing method and apparatus, an electronic device and a computer readable medium. The method includes: obtaining defect data of a wafer; obtaining position data of fail bits of the wafer; determining a defect area of a storage block in the wafer according to the defect data; determining a fail bit count of the storage block in the wafer according to the position data of the fail bits; processing the defect area and the fail bit count of each storage block in the wafer, so as to obtain a correlation coefficient; and determining an abnormal reason for the fail bits of the wafer according to the correlation coefficient.