Wafer Defect Forecasting via Frequency Domain Analysis
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Solution Overview
Problem
Conventional methods for forecasting wafer defects in semiconductor fabrication are inaccurate and time-consuming, often relying on trial-and-error approaches and image-based comparisons that are not effective in identifying defect-prone areas in IC layouts.
Innovation Solution
The method involves conducting frequency domain analysis on wafer defect images to extract principal components, disregarding noise such as rotation and locational offsets, and using a Modified Naive-Bayes classifier to forecast defect probabilities by comparing regions of interest (ROIs) in the IC layout, allowing for larger ROI sizes and more accurate defect identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional image-based comparison methods are used to forecast wafer defects, then the process is simple to implement, but the accuracy and effectiveness of defect identification is poor
Solution Approach 1:
The patent replaces conventional image-based comparison methods with frequency domain analysis using Fast Fourier Transform (FFT). This substitution transforms the defect analysis from spatial domain image matching to frequency domain pattern recognition, significantly improving defect prediction accuracy while systematically analyzing layout patterns and their corresponding defects through spectral characteristics
Solution Approach 2:
The patent changes the analysis parameters from spatial domain image properties to frequency domain characteristics. By applying FFT to convert layout images and defect images into frequency spectra, the method extracts meaningful frequency components that represent recurring pattern characteristics, enabling more accurate defect forecasting through parameter transformation
2Productivity
If trial-and-error approaches are used for defect forecasting, then the method is easy to apply, but it is time-consuming and inefficient
Solution Approach 1:
The patent replaces trial-and-error approaches with systematic frequency domain analysis. By using FFT to transform both layout and defect images into frequency spectra, the method enables direct comparison of frequency components to identify defect-prone patterns, eliminating the need for iterative trial-and-error testing and significantly improving forecasting efficiency
Solution Approach 2:
The patent performs preliminary frequency domain transformation of layout images before defect analysis. By pre-computing the frequency spectra of layout patterns and storing them for reference, the method enables rapid comparison with actual defect patterns during forecasting, reducing analysis time and improving productivity
3Measurement precision
If small ROI sizes are used in conventional methods, then the analysis is computationally simpler, but the ability to identify defect-prone areas is limited
Solution Approach 1:
The patent replaces spatial domain ROI analysis with frequency domain spectral analysis. By transforming images to frequency domain using FFT, the method can analyze larger spatial regions without proportionally increasing computational complexity, as the frequency transformation consolidates spatial information into spectral components that can be efficiently compared
Solution Approach 2:
The patent transitions from two-dimensional spatial ROI analysis to two-dimensional frequency spectrum analysis. This dimensional transformation in the frequency domain allows for more effective pattern recognition and defect identification, as frequency components reveal recurring layout patterns that may span large spatial areas but appear as distinct spectral features
Data Source
AI summary
Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.


