Hierarchical Clustering for Semiconductor Wafer Defect Detection
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Solution Overview
Problem
Existing methods for detecting and classifying defects in semiconductor wafers, such as spatial filtering and spatial randomness tests, face limitations in detecting scratch-shaped patterns with noise, and require extensive computational time for cluster calculation in hierarchical clustering.
Innovation Solution
A method using hierarchical clustering (HC) for defect detection and classification, which involves acquiring raw data, removing clusters that do not satisfy tuning parameters, and employing a random forest classifier to automate failure detection with minimal samples, even when new patterns occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If spatial filtering methods (average filter or median filter) are used to remove noise, then noise removal performance is improved, but the ability to detect scratch-shaped patterns (thin and long straight lines or round lines) deteriorates when noise is present
Solution Approach 1:
The patent segments the wafer map into multiple clusters using hierarchical clustering algorithm, where each cluster represents a distinct failure pattern type. This segmentation allows scratch-shaped patterns to be identified as separate clusters from noise, resolving the contradiction between noise removal and scratch detection capability
Solution Approach 2:
The patent applies partial action by selectively removing only those clusters that do not meet the predetermined threshold criteria for systematic failure patterns. This partial removal approach preserves scratch-shaped patterns while eliminating random noise, avoiding excessive filtering that would remove valid defect signals
2Measurement precision
If hierarchical clustering is used for failure pattern detection, then classification accuracy is improved, but computational time for cluster calculation increases
Solution Approach 1:
The patent performs preliminary actions by pre-calculating the hierarchical clustering structure and storing the cluster relationships in a dendrogram before actual failure detection. This preliminary preparation enables rapid classification of new wafer maps without repeating the full clustering computation, thus improving accuracy while reducing computational time for production use
Solution Approach 2:
The patent extracts only the essential cluster information and threshold criteria from the hierarchical clustering process, separating the computationally intensive clustering calculation from the routine failure detection task. This extraction allows the system to maintain high classification accuracy while minimizing repeated computational overhead
3Reliability
If supervised learning is used for failure pattern classification, then systematic failure detection is improved, but the ability to classify unknown failure patterns deteriorates
Solution Approach 1:
The patent inverts the traditional supervised learning approach by using unsupervised hierarchical clustering to automatically discover failure patterns without predefined labels. This inversion allows the system to detect both known systematic failures and previously unknown failure patterns, achieving both reliability and adaptability simultaneously
Data Source
AI summary
Disclosed is a method for semiconductor wafer pattern detection and classification using hierarchical clustering (HC). The method for semiconductor wafer pattern detection and classification is performed by a computing device including at least a processor and includes acquiring raw data; detecting a failure pattern of a target semiconductor wafer; and classifying the failure pattern of the target semiconductor wafer, and the detecting of the failure pattern includes removing a cluster that does not satisfy a first tuning parameter through the hierarchical clustering (HC); and determining that the target semiconductor wafer is normal when the cluster that satisfies the first tuning parameter is absent. The classifying of the pattern includes isolating a wafer previously identified to be defective into single patterns that satisfy a second tuning parameter, extracting a feature, and classifying the pattern through supervised learning.