Semiconductor Wafer Defect Inspection Using Chip-Sized Reference Marks
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Solution Overview
Problem
In semiconductor wafer processes, defects in wafers with inferior quality, such as SiC and GaN wafers, are not adequately detected, leading to inefficiencies and reduced yield rates due to the inability to accurately inspect and reject defective wafers early on, which can adversely affect device characteristics.
Innovation Solution
A defect inspection method that involves forming marks on semiconductor wafers corresponding to device chip sizes, allowing for defect detection and information gathering during or before the wafer process, enabling early-stage detection and improving yield rates by recognizing defects on a chip basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional defect inspection methods are used on wafers with inferior quality, then inspection time and resources are wasted on devices that will ultimately fail, but defect detection accuracy remains insufficient
Solution Approach 1:
The patent performs defect inspection at an early stage in the wafer process, before device fabrication is complete. By inspecting the wafer substrate early and identifying defects at the mark formation stage rather than after device manufacturing, the system detects defects before they propagate through subsequent processing steps, thereby improving detection accuracy while avoiding waste of time on devices that will ultimately fail
Solution Approach 2:
The patent segments the wafer inspection process by introducing marks that define specific inspection regions corresponding to individual device chips. This segmentation allows the inspection system to focus on specific areas of interest rather than scanning the entire wafer surface, improving defect detection accuracy for critical regions while reducing overall inspection time through targeted examination
2Productivity
If wafer inspection is performed late in the process, then fewer resources are wasted on defective devices, but defects cannot be detected early enough to improve yield rate
Solution Approach 1:
The patent performs defect inspection at an early stage in the wafer process, before device fabrication is complete. By inspecting the wafer substrate early and identifying defects at the mark formation stage rather than after device manufacturing, the system detects defects before they propagate through subsequent processing steps, thereby improving detection accuracy while avoiding waste of time on devices that will ultimately fail
Solution Approach 2:
The patent implements a feedback mechanism where defect inspection results are used to immediately identify and reject defective wafers or regions. The inspection system provides feedback about defect locations and characteristics, enabling real-time process control and early rejection of defective devices, which improves yield rate by preventing defective devices from progressing through the manufacturing process
3Reliability
If comprehensive defect inspection is performed on all wafers, then defect detection coverage is improved, but inspection cost and complexity increase
Solution Approach 1:
The patent segments the wafer inspection process by introducing marks that define specific inspection regions corresponding to individual device chips. This segmentation allows the inspection system to focus on specific areas of interest rather than scanning the entire wafer surface, improving defect detection accuracy for critical regions while reducing overall inspection time through targeted examination
Solution Approach 2:
The patent introduces marks as intermediary elements that facilitate the inspection process. These marks serve as reference points and region identifiers that simplify the inspection system's task of locating and examining specific areas on the wafer. The marks act as mediators between the inspection system and the wafer surface, reducing complexity by providing clear structural references for automated inspection
Data Source
AI summary
A defect inspection method according to the present invention is a defect inspection method for inspecting a defect of a semiconductor wafer, including the steps of: (a) forming a mark on a semiconductor wafer that is an inspection object, the mark corresponding to the size of a device chip that will be obtained from the semiconductor wafer, the mark being formed with respect to a predetermined device chip on the semiconductor wafer; and (b) during a predetermined process included in a semiconductor wafer process or before the semiconductor wafer process, performing a defect inspection on the semiconductor wafer and recognizing defect information based on the mark as a reference.