Wafer Defect Segregation via Net Connectivity Analysis
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Solution Overview
Problem
The increasing number of detected defects and high false alarm ratio during wafer inspection in integrated circuit manufacturing, due to shrinking device geometries, lead to inefficiencies and potential misses of real defects, resulting in higher costs and lower yields.
Innovation Solution
A method that creates a defect map by merging defects across multiple dies, determines connectivity between layout shapes, and groups defects based on electrical connectivity, using layout and netlist data to prioritize and select defect groups, thereby differentiating between real and false alarms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer inspection is performed on all detected defects, then defect detection completeness is improved, but inspection time and resources increase dramatically
Solution Approach 1:
The patent segments defects into different categories based on their characteristics and locations. By grouping defects that share common features (such as being in the same location across multiple dies or having similar geometric properties), the inspection process can focus on representative defects from each group rather than examining every individual defect, thereby reducing inspection time while maintaining detection completeness.
Solution Approach 2:
The patent performs preliminary analysis of defect data before full inspection by identifying patterns, correlations, and representative defects. This preliminary action includes analyzing defect locations across multiple dies, geometric characteristics, and process parameters to pre-select which defects require detailed inspection, thus avoiding time-consuming inspection of obviously non-critical defects.
2Reliability
If wafer inspection is performed on all detected defects, then defect detection completeness is improved, but resource consumption increases
Solution Approach 1:
By segmenting defects into categories and groups based on their characteristics, the patent enables resource allocation to be focused on specific defect groups that are most likely to be critical. This selective approach reduces the total resources required for inspection compared to examining all defects individually, while still maintaining comprehensive coverage of critical defect types.
Solution Approach 2:
The patent changes inspection parameters dynamically based on defect characteristics. Instead of using uniform inspection resources for all defects, the system adjusts inspection depth, methodology, and resource allocation based on defect severity, location, and pattern analysis, thereby optimizing resource consumption while maintaining detection effectiveness.
3Productivity
If device geometries are shrunk to increase integration, then IC functionality is improved, but false alarm ratio increases
Solution Approach 1:
The patent applies local quality analysis by examining defect characteristics in specific local contexts rather than using uniform criteria across the entire wafer. By analyzing defects in the context of their specific locations, surrounding structures, and process variations, the system can distinguish between actual defects and measurement artifacts more effectively, thereby reducing false alarms while maintaining the ability to detect real defects in shrunk geometries.
Solution Approach 2:
The patent applies partial action by focusing inspection efforts on specific defect types and locations that are most relevant to device functionality. Rather than applying excessive inspection to all areas uniformly, the system selectively intensifies inspection where needed based on device criticality and defect patterns, reducing overall false alarm rates while maintaining detection capability for critical defects.
4Productivity
If high false alarm ratio is accepted to maintain inspection speed, then inspection efficiency is improved, but real defects may be missed
Solution Approach 1:
The patent performs preliminary analysis to establish baseline defect patterns and characteristics before final defect determination. By pre-processing defect data to identify patterns, correlations with process parameters, and representative defects, the system can make more accurate decisions about which defects are real versus false alarms, thereby maintaining both inspection efficiency and detection accuracy.
Solution Approach 2:
The patent implements feedback mechanisms where inspection results are continuously analyzed and used to refine inspection criteria and parameters. By feeding back information about detected defects, false alarms, and process variations into the inspection system, the methodology can dynamically adjust its approach to maintain high accuracy while preserving inspection efficiency, avoiding the need to accept high false alarm rates.
Data Source
AI summary
A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.