Wafer Defect Classification via Simulated Layout

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Solution Overview

Problem

Current methods for classifying defects in semiconductor wafers cannot identify the type of defect, such as a lead, MOS, or electrode, without the layout of the chip, limiting the ability to improve manufacturing processes.

Innovation Solution

A method and system that utilize a simulated layout corresponding to the real layout of the chips, allowing for the classification of defects by translating defect-free images into a simulated layout and comparing them with the simulated layout of the chip, enabling the identification of semiconductor structures corresponding to defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If scanned images are compared to identify defect positions, then defect location can be determined, but defect type classification cannot be achieved

Engineering Contradiction:

Improvedefect location identificationVSAvoiddefect type information

Core Design Contradiction:

Measurement precisionVSLoss of information

Solution Approach 1:

The patent creates a simulated layout that copies the essential structural information of the chip from the defect-free scanned image. This simulated layout serves as a reference model that preserves the geometric and topological characteristics of the chip structure, enabling defect type classification by comparing defective images against this synthesized reference rather than requiring the original design layout

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The simulated layout acts as an intermediary between the scanned image and the actual chip design. It translates the visual information from the defect-free scanned image into a structured representation that can be used for defect classification, bridging the gap between image processing and defect type identification without requiring access to the original design files

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of information

If manual layout drawing or auto edge tracing is used to create simulated layout, then defect classification becomes possible, but processing time and complexity increase

Engineering Contradiction:

Improvedefect type informationVSAvoidlayout generation time

Core Design Contradiction:

Loss of informationVSLoss of time

Solution Approach 1:

The system uses the defect-free scanned image itself as the source material to generate the simulated layout through automated edge tracing algorithms. The algorithm processes the existing image data to extract structural information and construct the simulated layout automatically, eliminating the need for manual drawing while maintaining accuracy. The process leverages the input image's own characteristics to produce the required output without external intervention

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent replaces manual layout drawing with automated computational algorithms that process scanned images to generate simulated layouts. The edge tracing algorithm automatically extracts structural boundaries and generates the layout representation through computational geometry operations, substituting the mechanical process of manual sketching with an automated digital process that is both faster and more consistent

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If real layout is not available, then wafer scanning can be performed, but defect feature identification is limited

Engineering Contradiction:

Improvewafer scanning capabilityVSAvoidsemiconductor structure information

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

The system performs preliminary action by generating the simulated layout from defect-free scanned images before defect analysis is required. This pre-generated simulated layout serves as a ready-to-use reference for classifying defects in subsequent scanning operations, eliminating the need to wait for the actual chip design layout to become available while maintaining the ability to identify defect features and semiconductor structures

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables accurate classification of defects, improving the manufacturing process by identifying specific semiconductor structures associated with defects, even when the real layout is not available, thereby increasing semiconductor yield and efficiency.

Implementation Method 1

After a wafer is scanned by a charged particle beam, there are numerous scanned images respectively corresponds to numerous chips of the wafer

Methodology Applied

Scientific EffectCharged particle beam scanning: Electron Beam

Data Source

PatentUS9436988B2Method and system of classifying defects on a wafer

Publication Date: 2016.09.06 ASML NETHERLANDS BV

AI summary

A method of classifying the defects on a wafer having some same chips and corresponding system is provided. After receiving images formed by scanning the wafer using a charged particle beam, these images are examined such that both defective images and defect-free images are found. Then, the defect-free images are translated into a simulated layout of the chip, or a database is used to provide the simulated layout of the chip. Finally, the defects on the defective images are classified by comparing the images with the simulated layout of the chip. The system has some modules separately corresponds to the steps of the method.