Semiconductor Wafer Defect Detection via Simulated Layout Comparison
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Solution Overview
Problem
Detecting defects in small features of semiconductor wafers during processing is difficult and costly, often leading to undetected defects in integrated circuits.
Innovation Solution
A semiconductor wafer defect detection system that captures images of the wafer, generates simulated integrated circuit layouts using machine learning, and compares them to reference layouts to identify defects, utilizing an imaging system, simulated layout generation, defect locator, and analyzer to quickly and accurately detect defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional defect review methods are used, then the process is simple to implement, but the measurement precision and detection accuracy are insufficient for very small features
Solution Approach 1:
The patent creates a simulated layout copy of the semiconductor wafer based on design data, then compares this simulation with the actual wafer images to detect defects. This copying approach allows high-precision defect detection without requiring complex direct imaging systems, as the simulation serves as a reference template for comparison.
Solution Approach 2:
The patent introduces a simulated layout as an intermediary between the actual wafer and the detection system. Instead of directly analyzing the wafer with complex equipment, the system compares wafer images against the simulated layout, which acts as a mediator that simplifies the detection process while maintaining high accuracy.
2Productivity
If traditional defect review methods are used, then the equipment requirements are minimal, but the productivity and time efficiency are poor
Solution Approach 1:
The patent performs preliminary action by pre-generating a simulated layout based on the design data before actual defect detection is needed. This simulation is created in advance and stored as a reference, allowing rapid comparison with wafer images during the defect review process, thus significantly reducing detection time.
Solution Approach 2:
The patent replaces manual or slow mechanical defect inspection processes with an automated computational comparison system. The simulated layout generation and image comparison are performed through computer processing, which is much faster than traditional physical inspection methods, thereby improving productivity.
3Reliability
If traditional defect review methods are used, then the resource consumption is low, but the reliability and completeness of defect detection are insufficient
Solution Approach 1:
The patent uses a simulated layout copy that is generated from design data to serve as a reference for defect detection. This virtual copy allows comprehensive comparison with actual wafer images, improving detection reliability without requiring extensive physical sampling or multiple inspection stages, thus controlling resource consumption.
Solution Approach 2:
The simulated layout is prepared in advance using computational resources, creating a comprehensive reference model that can be efficiently compared against wafer images. This preliminary generation of the simulation allows for reliable defect detection while minimizing the need for repeated or extensive resource-intensive inspection processes.
Data Source
AI summary
A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.