Wafer-to-Design Image Analysis for Automated SEM Qualification
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Solution Overview
Problem
The traditional process of qualifying images of circuit patterns on wafers using a scanning electron microscope (SEM) is labor-intensive and time-consuming, requiring manual effort and analysis.
Innovation Solution
A polygon-based layout analysis method combined with automated gauge placement, image-to-GDS alignment, and layer/gauge-dependent judgment, enabling fully automated SEM image qualification without reliance on SEM operators, and allowing for standardized image qualification across different applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual image qualification process is used, then measurement accuracy can be maintained through expert analysis, but processing time and labor intensity increase significantly
Solution Approach 1:
The system enables automated self-qualification of SEM images through algorithmic analysis. The WDIA module automatically performs image acquisition, alignment with GDS data, feature extraction, and qualification judgment without requiring manual operator intervention, thereby reducing processing time while maintaining accuracy through standardized automated procedures
Solution Approach 2:
The patent replaces manual mechanical analysis processes with automated computational systems. The manual image qualification process is substituted with an automated WDIA module that uses computer vision algorithms, image processing techniques, and automated measurement systems to analyze and qualify SEM images, eliminating the need for manual operator analysis
2Adaptability or versatility
If manual image qualification is performed, then flexibility in handling different applications is maintained, but standardization and efficiency are reduced
Solution Approach 1:
The WDIA module is designed as a universal automated system that can handle multiple different applications and image types. The system incorporates configurable parameters and algorithms that can be adapted to various semiconductor manufacturing inspection tasks, providing both standardization for efficiency and flexibility for different applications through a single integrated platform
Solution Approach 2:
The system achieves adaptability through parameter configuration rather than structural changes. The automated qualification process allows modification of measurement parameters, thresholds, and analysis criteria to suit different applications, enabling the same automated system to handle diverse inspection requirements while maintaining high processing efficiency
3Productivity
If automated image qualification is implemented, then processing speed and standardization improve, but system complexity increases
Solution Approach 1:
The automated qualification system is divided into distinct functional modules: image acquisition module, alignment module, feature extraction module, and qualification judgment module. This segmentation allows each component to be optimized independently and simplifies the overall system architecture, making the complex automated process more manageable and maintainable while maintaining high processing speed
Data Source
AI summary
A method includes obtaining a layout of a circuit pattern implemented on a semiconductor wafer, and identifying one or more polygons in the layout based on a length criteria. One or more measurement gauges are placed on the identified polygons to thereby obtain measured polygons. A scanning electron microscope (SEM) image of the circuit pattern is obtained. The SEM image is aligned with the layout including the measured polygons. A critical dimension of one or more objects in the SEM image is measured. The one or more objects correspond to the one or more polygons. Based on the measured critical dimension, it is determined whether the circuit pattern is acceptable.