Wafer Design Image Coordinate Mapping Automation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current techniques for generating wafer design to image mappings are prone to errors due to manual correlation processes, which can result in positioning inaccuracies and mismatched wireframe designs with wafer images, making it difficult to accurately locate small defects in wafer images.
Innovation Solution
A system and method for automatically generating a wafer image to design coordinate mapping using a computer processor, where a design and image of a wafer are processed to create an accurate coordinate mapping, reducing user error and improving alignment through pattern matching and algorithmic processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual correlation techniques are used to generate wafer design to image mappings, then user flexibility and system simplicity are maintained, but positioning accuracy and mapping reliability deteriorate due to user error and stage positioning inaccuracies
Solution Approach 1:
The system performs self-alignment by automatically generating wafer design to image mappings through algorithmic processing of design data and image data, eliminating the need for manual user correlation. The computer processor independently computes coordinate mappings without human intervention, thereby improving mapping accuracy while avoiding the complexity of manual operation interfaces.
Solution Approach 2:
The patent replaces the manual mechanical correlation process with an automated computational system. Instead of users manually correlating design coordinates with image coordinates through interactive interfaces, a computer processor automatically generates coordinate mappings by processing design data and image data algorithmically, substituting human-operated mechanical interaction with automated computational processing.
2Measurement precision
If automated coordinate mapping generation is implemented, then mapping accuracy and defect location precision are improved, but device complexity and processing requirements increase
Solution Approach 1:
The system performs self-alignment by automatically generating wafer design to image mappings through algorithmic processing of design data and image data, eliminating the need for manual user correlation. The computer processor independently computes coordinate mappings without human intervention, thereby improving mapping accuracy while avoiding the complexity of manual operation interfaces.
Solution Approach 2:
The patent creates a computational copy of the wafer design coordinates and matches it with the image coordinates through automated processing. The computer processor generates a digital representation of the design coordinate system and aligns it with the captured image coordinate system, enabling accurate defect location without manual intervention.
Data Source
AI summary
A system, method, and computer program product are provided for automatically generating a wafer image to design coordinate mapping. In use, a design of a wafer is received by a computer processor. In addition, an image of a wafer fabricated from the design is received by the computer processor. Further, a coordinate mapping between the design and the image is automatically generated by the computer processor.


