Wafer Dicing Abnormality Integration for Inspection Efficiency
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Solution Overview
Problem
In semiconductor manufacturing, dicing processes often result in chipping and misalignment issues that are not effectively utilized for inspection or processing improvements in post-stage inspection or processing apparatuses.
Innovation Solution
A processing information management system that includes an abnormality analyzer and integration system to generate and integrate abnormality occurrence data from sensor outputs, enabling effective utilization of chipping information for improved efficiency and speed in post-stage inspection or processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dicing is performed with a blade, then semiconductor devices are divided into individual chips, but chipping occurs on cut surfaces and misalignment happens between reference lines and actual cutting positions
Solution Approach 1:
The patent applies preliminary action by performing dicing processing before inspection, and capturing abnormality information (chipping, misalignment) during the dicing process itself. This allows the inspection apparatus to pre-know which chips may have defects, enabling targeted inspection and efficient sorting of normal and abnormal chips before they reach subsequent processing stages.
Solution Approach 2:
The patent implements feedback by transmitting abnormality information from the dicing apparatus to the inspection apparatus. The inspection apparatus receives real-time or near-real-time data about chipping and misalignment occurrences, uses this information to adjust inspection parameters, and provides feedback for improving dicing quality in subsequent batches.
2Productivity
If abnormality information from dicing is not utilized, then inspection and processing efficiency remain low, but implementing utilization requires integration systems and data management infrastructure
Solution Approach 1:
The patent applies universality by designing the inspection apparatus to perform multiple functions: it inspects chips for defects, receives and processes abnormality information from the dicing apparatus, integrates this information with inspection results, and outputs comprehensive quality data. This multi-functional approach consolidates what could be separate systems into one integrated apparatus, reducing overall system complexity.
Solution Approach 2:
The patent merges the abnormality information management function with the inspection apparatus. Instead of having a separate data management system, the inspection apparatus directly receives, processes, and integrates dicing abnormality information with its inspection results. This consolidation simplifies the information flow and reduces the complexity of the overall system architecture.
3Reliability
If chipping and misalignment are detected but not effectively utilized, then quality control remains reactive, but implementing effective utilization requires real-time data integration and analysis capabilities
Solution Approach 1:
The patent implements feedback by creating a closed-loop quality control system. Abnormality information from dicing is fed back to the inspection apparatus, which uses this information to adjust its inspection strategy and provide feedback that can influence subsequent dicing processes. This automated feedback loop transforms quality control from a reactive to a proactive system.
Solution Approach 2:
The inspection apparatus performs self-service by automatically receiving, processing, and utilizing abnormality information without requiring manual intervention. The system autonomously integrates dicing data with inspection results and generates comprehensive quality reports, reducing the need for manual data collection and analysis while improving reliability.
Data Source
AI summary
According to one embodiment, a processing information management system includes: an abnormality analyzer configured to generate abnormality occurrence data of a target wafer based on processing location information, the processing location information collected based on a first sensor outputting a first sensor signal according to a detected processing state, the first sensor provided in a wafer processing apparatus; and an integration system configured to integrate the abnormality occurrence data into wafer map data corresponding to the target wafer.