Wafer Dicing and Bonding Sequence to Prevent Chip Warpage
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Solution Overview
Problem
As the number of memory cells stacked in a semiconductor device increases, the substrate can become bent, leading to deteriorated electric characteristics, and existing methods struggle to maintain alignment and reliability in bonding processes, resulting in misalignment and unreliable electrical connections.
Innovation Solution
A method of manufacturing semiconductor devices involves forming structures on multiple wafers, separating and bonding chip regions through precise dicing processes to prevent warpage and misalignment, ensuring secure and reliable electrical connections by dividing wafers into multiple portions and bonding them in a staged manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells stacked in vertical direction increases, then data storage capacity increases, but substrate bending occurs and electric characteristics deteriorate
Solution Approach 1:
The patent divides the wafer into multiple regions (first chip regions, second chip regions, third chip regions) and processes them in separate stages. The wafer is segmented into first and second portions, with different chip regions separated at different stages. This segmentation prevents substrate bending by reducing the stress concentration that would occur if all memory cells were stacked simultaneously across the entire wafer, thereby maintaining electric characteristics while achieving high data storage capacity.
2Productivity
If multiple chip regions are separated and bonded in a single process, then productivity is high, but misalignment occurs and bonding reliability decreases
Solution Approach 1:
The patent segments the bonding process into multiple stages: first separating first chip regions from first chip regions, then separating second chip regions from second chip regions, and finally separating third chip regions from third chip regions. Each stage bonds a specific portion of the wafer, ensuring precise alignment. This staged approach maintains manufacturing precision while achieving high productivity through systematic processing of different wafer portions.
Solution Approach 2:
The patent performs preliminary separation of chip regions before bonding. The first chip regions are separated from the first wafer before bonding to the second wafer, and subsequent chip regions are separated and bonded in predetermined sequences. This preliminary action ensures that each bonding operation involves pre-positioned components, eliminating misalignment issues that would occur if all components were bonded simultaneously without prior positioning.
3Loss of time
If the entire wafer is processed at once, then manufacturing time is short, but warpage occurs and bonding reliability decreases
Solution Approach 1:
The patent divides the wafer processing into multiple time stages, with each stage handling specific chip regions. The first portion of the wafer is processed to separate and bond first chip regions, then the second portion is processed for second chip regions, and finally the third portion is processed for third chip regions. This segmentation prevents warpage by limiting the number of components processed simultaneously, thereby maintaining bonding reliability while achieving efficient manufacturing through parallel processing of different wafer portions.
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes: forming a first structure on a first wafer; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.