Semiconductor Wafer Dicing Boundary Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor wafer dicing methods often result in unintentional cutting or tearing during back grinding due to the fragility of kerf regions, which are intended to be sacrificed during the dicing process, leading to inefficiencies and potential damage to the wafer.
Innovation Solution
A dicing boundary structure is formed by filling cavities in the kerf regions with a filling material, such as deposited by chemical vapor deposition or sputtering, creating a void that concentrates stress and facilitates controlled separation of chip regions without the need for machining scribe lines with blades, thereby reducing the risk of unintended cuts during back grinding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dicing methods are used with blades to form scribe lines, then chip separation can be achieved, but unintentional cutting or tearing occurs during back grinding due to fragility of kerf regions
Solution Approach 1:
The dicing boundary structure is formed in advance during wafer fabrication, creating pre-defined separation zones with different mechanical properties before dicing occurs. This preliminary structuring eliminates the need for blade scribing and prevents unintended cutting during back grinding by concentrating stress at the pre-formed boundaries.
Solution Approach 2:
The mechanical blade-based scribing system is replaced with a stress-concentration-based separation system. Instead of using physical blades to cut through the wafer, the invention uses differential stress distribution created by the dicing boundary structure (with different Young's moduli) to achieve clean separation during back grinding.
2Productivity
If kerf regions are made fragile to facilitate separation, then chip regions can be easily separated, but unintentional cutting or tearing occurs during back grinding
Solution Approach 1:
The dicing boundary structure introduces local variations in material properties (different Young's moduli) at specific locations where separation is desired. The kerf regions are selectively structured with alternating high and low Young's modulus materials, creating localized stress concentration zones that guide crack propagation only at intended separation lines during back grinding.
Solution Approach 2:
The dicing boundary structure employs composite materials with different mechanical properties (different Young's moduli) arranged in alternating layers or patterns. This composite structure creates differential stress distribution that concentrates tensile stress at the interfaces between high and low modulus regions, enabling controlled separation while preventing unintended cutting in other areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise and efficient separation of semiconductor chips from the wafer, reducing the likelihood of unintentional cuts or fractures during dicing and enabling the formation of integrated circuits with improved surface quality and reduced material waste.
Implementation Method 1
filling a first cavity formed in a device layer with a filling material, such as the filling material being deposited by chemical vapor deposition or sputtering
Implementation Method 2
filling a first cavity formed in a device layer with a filling material, such as the filling material being deposited by chemical vapor deposition or sputtering
Data Source
AI summary
According to one embodiment, a semiconductor wafer includes a plurality of chip regions, a plurality of chip regions, a device layer, a first structure, and a second structure. The device layer includes an integrated circuit formed in each of the chip regions. The first structure is formed in the kerf region by filling a first cavity with a first filling material. The first cavity extends vertically with respect to a surface of a semiconductor substrate. The second structure is formed in the device layer by filling a second cavity with a second filling material. The second cavity extends vertically with respect to the surface of the semiconductor substrate.