Semiconductor Wafer Dicing Crack Prevention Using Peripheral Trenches
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Solution Overview
Problem
The fabrication of HEMT devices using epitaxial growth processes faces challenges such as substrate cleavage, chip breakage, and crack propagation during wafer dicing due to the mechanical strength limitations of type III-V semiconductor materials, which can lead to device failure and increased costs from complex etching processes.
Innovation Solution
The method involves forming crack stopping trenches in the type III-V semiconductor layer with a filler material that extends to the base substrate, oriented antiparallel to the preferred cleavage planes, to prevent crack propagation during die singulation, using a silicon substrate with a (111) plane and {110}, {011}, {101} crystallographic planes, and filling these trenches with materials like semiconductor oxides or metals to enhance mechanical strength and reduce cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mechanical sawing or laser cutting is performed along the mechanical scribe line to separate the wafer into individual dies, then die singulation is achieved, but chip breakage and crack propagation occur due to the mechanical strength limitations of type III-V semiconductor materials
Solution Approach 1:
The patent divides the continuous wafer into discrete die regions by forming trenches along the periphery of each die. These trenches segment the wafer structure, creating physical boundaries that allow individual dies to be separated through sawing or laser cutting without causing cracks to propagate across the entire wafer or into adjacent dies. The trenches act as isolation barriers that contain mechanical stress and crack propagation within localized regions.
Solution Approach 2:
The patent performs preliminary trench formation along the periphery of each die before the final singulation step. By pre-forming these protective trenches that extend through the type III-V semiconductor layer and into the substrate, the structure is prepared in advance to resist crack propagation during subsequent mechanical sawing or laser cutting operations, preventing chip breakage before it occurs.
2Reliability
If separate etching steps are used to remove type III-V semiconductor material prior to mechanical dicing, then chip breakage is reduced, but the process becomes very complex and costly and may lead to increase of particle contamination on the device
Solution Approach 1:
The patent combines the trench formation step with the peripheral material removal process. By forming trenches along the die periphery that extend into the substrate during the same processing step, the invention eliminates the need for separate etching steps that would otherwise be required to remove material before dicing. This merged approach reduces process complexity and the associated particle contamination risks while still providing crack propagation resistance.
3Quantity of substance
If type III-V semiconductor material is removed by laser processes prior to mechanical sawing, then material removal is achieved, but chip breakage strength decreases
Solution Approach 1:
The patent applies localized trench formation only along the periphery of each die rather than removing material uniformly across the entire wafer surface. This local quality approach concentrates the material removal and structural modification specifically at the boundaries where crack propagation is most likely to occur, while preserving the full thickness and strength of the type III-V semiconductor material in the active device regions, thereby maintaining chip breakage strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents cracks from reaching active devices, enabling low-cost, low-defect die singulation with minimal processing steps, and can integrate functional elements like diodes or electrical connectors within the trenches, improving the mechanical strength and reliability of semiconductor chips.
Implementation Method 1
a first trench is formed by an etching process and semiconductor material that is exposed from the openings of the mask from the type III-V semiconductor layer is removed
Data Source
Figure 1~1B
Figure 2
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AI summary
In an embodiment, a method of forming a semiconductor device comprises providing a semiconductor base substrate comprising a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface and forming a first trench that vertically extends from an upper surface of the first type III-V semiconductor layer at least to the planar growth surface, wherein the first trench has a length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.