Silicon Wafer Dicing Etching Sequence to Prevent Chip Edge Chipping

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Solution Overview

Problem

The existing methods for dividing silicon wafers using plasma etching often result in chipping at the edges of device chips, which lowers the quality of the chips due to isotropic etching during the Bosch process.

Innovation Solution

A device chip manufacturing method that alternately repeats isotropic etching using CF4 or SF6 gas and passivation film coating with C4F8 gas to form deep grooves, followed by anisotropic etching using a mixed gas of SF6 and O2 to reach the back surface of the wafer, preventing chipping at the edges of the division grooves.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If isotropic etching is used to dig deeper grooves in the Bosch process, then the grooves reach the back surface of the wafer, but chipping is formed at the edges of the division grooves

Engineering Contradiction:
Improvegroove depthVSAvoidchipping at groove edges
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The etching process is segmented into two distinct stages: first, isotropic etching is used to create deep grooves that approach the back surface, then anisotropic etching is used to precisely finish the groove edges at the back surface. This segmentation allows each etching method to be used where it is most effective, preventing chipping while achieving the required groove depth.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The Bosch process uses periodic alternation between etching steps (isotropic) and protective film formation steps. This periodic action allows the grooves to be deepened progressively while the protective film prevents lateral etching and protects the groove walls, ultimately preventing chipping at the edges when the grooves reach the back surface.

Inventive Principle:
Principle #19Periodic action

2Ease of manufacture

If plasma etching is used to divide the silicon wafer, then division grooves are formed, but chipping occurs at the bottom surface edges

Engineering Contradiction:
Improvewafer divisionVSAvoidedge quality at chip bottom
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The etching parameters are changed between two different etching methods: isotropic etching parameters are used first to achieve deep groove formation, then anisotropic etching parameters are used to precisely control the final groove edges at the back surface. This parameter change ensures clean edges without chipping while maintaining ease of wafer division.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures that chipping is not left at the edges of device chips, thereby maintaining the quality of the chips by avoiding isotropic etching at the back surface of the silicon wafer.

Implementation Method 1

isotropic etching using a plasma of a CF4 gas or an SF6 gas

Methodology Applied
Scientific EffectPlasma etching (isotropic): Plasma

Implementation Method 2

coating of regions exposed by the isotropic etching with a passivation film by use of a plasma of a C4F8 gas

Methodology Applied
Scientific EffectPlasma deposition: Plasma

Implementation Method 3

anisotropic etching by use of a plasma of a mixed gas of SF6 and O2

Methodology Applied
Scientific EffectPlasma etching (anisotropic): Plasma

Data Source

PatentUS11990371B2Device chip manufacturing method
Publication Date: 2024.05.21 DISCO CORP
  • US11990371B2 patent drawing
  • US11990371B2 patent drawing
  • US11990371B2 patent drawing

AI summary

A device chip manufacturing method for dividing a silicon wafer formed with devices in each of regions of a front surface partitioned by a plurality of streets includes coating the front surface of the silicon wafer with a resist film, exposing the silicon wafer by removing the resist film in regions along the streets, forming deep grooves by alternately repeating isotropic etching and coating with a passivation film, and subjecting bottom portions of the deep grooves to anisotropic etching to form division grooves, thereby dividing the silicon wafer.