Semiconductor Wafer Dicing with Vertical Dielectric Edge Protection
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Solution Overview
Problem
The dicing process of semiconductor wafers with ultra-low dielectric constant layers faces challenges such as extended etching times, metal sputtering, and delamination risks, which can lead to performance degradation and moisture penetration in the dielectric layers.
Innovation Solution
A method involving a hard mask formation with dielectric layers and a vertical dielectric layer to protect the ultra-low dielectric constant layers during etching and chemical treatment, using reactive ion plasma etching and temporary masks to independently etch dicing and contact regions, and depositing silicon nitride or silicon oxide to enhance adherence and prevent delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If etching is performed simultaneously to form dicing lines and expose metal blocks, then both operations are completed in one step, but etching time is extended and metal sputtering occurs
Solution Approach 1:
The patent divides the etching process into two separate sequential steps: first etching dicing lines through the hard mask, then etching openings to expose metal blocks. This segmentation prevents simultaneous etching of both features, thereby reducing total etching time and preventing metal sputtering that would occur if both were etched at the same time.
2Manufacturing precision
If a thick photosensitive resin mask is used to expose metal blocks, then metal blocks are properly exposed, but the mask has poor adherence and causes delamination during removal
Solution Approach 1:
The patent introduces a thin adhesion promoter layer deposited between the photosensitive resin mask and the hard mask surface. This intermediary layer improves the adherence of the mask, preventing delamination during removal while still allowing precise exposure of metal blocks through the mask openings.
3Ease of operation
If chemical treatment is applied to clean metal contacts after mask removal, then metal contacts are cleaned, but delamination occurs in ultra-low dielectric constant layers
Solution Approach 1:
The patent modifies the chemical treatment parameters by using a plasma-based cleaning process with controlled chemistry and power settings. This allows effective cleaning of metal contacts while minimizing the risk of delamination in ultra-low dielectric constant layers by carefully controlling the treatment severity.
4Manufacturing precision
If dicing lines are etched through all layers including interconnection network, then complete dicing lines are formed, but etching time is extended beyond what is needed for metal block exposure
Solution Approach 1:
The patent segments the etching process into two distinct steps: first etching dicing lines through the hard mask to complete depth, then separately etching openings to expose metal blocks. This allows the dicing lines to be fully formed in the first step without extending the overall process time, as the second step only requires creating openings to metal blocks rather than etching through all layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method prevents delamination and metal dispersion, reduces etching time, and maintains the integrity of ultra-low dielectric constant layers, ensuring the performance and reliability of semiconductor devices.
Implementation Method 1
a first etching producing an opening in the dicing region via said layers of the interconnection network
Implementation Method 2
cleaning the uncovered surface of the metal contact using a chemical treatment
Implementation Method 3
depositing silicon nitride or silicon oxide to enhance adherence and prevent delamination
Data Source
AI summary
A wafer includes a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region. A hard mask is formed having a pattern that defines a dicing line. The formation of the hard mask includes a first etching of an opening in the dicing region to expose the semiconductor substrate in the dicing region, a second etching of an opening in the contact region to expose a surface of a metal contact in the contact region, and a chemical treatment for cleaning the uncovered surface of the metal contact. A vertical dielectric layer is deposited to cover edges of the opening defining the dicing line. This layer is deposited before the chemical treatment is performed.