Semiconductor Wafer Dicing Evaluation Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wafer dicing processes are inefficient and unreliable due to the manual or machine-based visual inspection for defects like chips and cracks, leading to potential early failure of integrated circuits, as not all dice are inspected and damaged units can be delivered to customers.
Innovation Solution
Incorporating evaluation lines, such as loop-shaped conductive lines, UHF or RF antennas, or capacitive lines, in the scribe lines of semiconductor wafers, connected to evaluation circuits that assess the length and continuity of these lines to electronically detect defects and evaluate the dicing process, allowing for real-time feedback and potential rejection or acceptance of functional integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If visual inspection is used to detect defects in diced integrated circuits, then defect detection capability is provided, but the process becomes time-consuming and expensive
Solution Approach 1:
The patent applies preliminary action by placing evaluation lines on the wafer before dicing, so that defect detection capability is built into the structure in advance. After dicing, the evaluation lines on individual dies can be quickly evaluated to detect chips and cracks without requiring time-consuming visual inspection of each die edge.
Solution Approach 2:
The patent replaces the mechanical visual inspection process with an electrical evaluation system. Instead of manually or visually examining each die, electrical evaluation lines are used to automatically detect defects through electrical measurements, significantly reducing inspection time and cost.
2Measurement precision
If visual inspection is performed on all dice, then defect detection accuracy is improved, but the cost and time requirements increase significantly
Solution Approach 1:
The patent replaces slow visual inspection with rapid electrical evaluation of the evaluation lines. This substitution maintains high defect detection accuracy while dramatically increasing productivity, allowing all dice to be evaluated quickly without the bottlenecks of manual inspection.
Solution Approach 2:
The patent uses evaluation lines as electrical copies or proxies for the physical die structure. By evaluating the electrical properties of these lines rather than physically inspecting each die, the system achieves both high accuracy and high throughput.
3Productivity
If not all dice are inspected, then productivity is maintained, but defective integrated circuits may reach customers
Solution Approach 1:
The patent prepares evaluation lines on all dice in advance during wafer fabrication. This preliminary action enables complete inspection of all dice at high speed after dicing, ensuring that no defective units escape while maintaining full productivity.
Solution Approach 2:
By replacing physical inspection with electrical evaluation, the system can efficiently inspect 100% of dice without the time and cost constraints of visual methods, thereby ensuring complete quality assurance while maintaining productivity.
4Reliability
If evaluation lines are added to the wafer, then defect detection capability is enhanced, but device complexity increases
Solution Approach 1:
The evaluation lines serve multiple functions: they act as both structural elements during wafer processing and as defect detection sensors after dicing. This multi-functionality reduces the need for separate dedicated test structures, minimizing the increase in overall device complexity.
Solution Approach 2:
The patent uses existing conductive materials and line structures, changing their functional parameters rather than introducing entirely new components. The evaluation lines are integrated into the existing wafer architecture using standard fabrication processes, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables accurate, efficient, and automated detection of defects in the dicing process, reducing the likelihood of defective integrated circuits reaching customers and allowing for process adjustments, such as re-centering the blade, thereby improving the quality and reliability of the dicing process.
Implementation Method 1
evaluating their length comprises determining whether there is an electrical continuity between two ends of the loop-shaped conductive lines
Implementation Method 2
evaluating their length comprises generating an ambient electrical or magnetic field and sensing an AC voltage induced in the conductive lines
Implementation Method 3
evaluating their length comprises sensing a capacitance value of the capacitive lines
Data Source
AI summary
Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.