Wafer Dicing via Photolithography and Plasma Etching
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Solution Overview
Problem
Conventional semiconductor wafer dicing techniques require larger scribe lines, resulting in a reduced number of usable semiconductor dice and inefficient use of wafer space.
Innovation Solution
A photolithographic method is employed to separate semiconductor dice with smaller scribe lines (5 μm to 50 μm in width) and strategically placed bonding pads, allowing for increased gross die number by arranging scribe lines along or through the pads, and using anisotropic plasma etching to create deep trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional wafer dicing techniques (mechanical cleaving, laser dicing, sawing with diamond blade) are used, then the wafer can be divided into individual dice, but the scribe lines become larger and the gross die number decreases
Solution Approach 1:
The patent replaces conventional mechanical dicing methods (mechanical cleaving, sawing with diamond blade) and laser dicing with a photolithographic patterning process followed by plasma etching. This substitution enables precise control of scribe line width at the micro-scale (5-50 μm), significantly reducing the scribe line area and increasing the gross die number per wafer.
Solution Approach 2:
The patent changes the critical parameter of scribe line width from the conventional range (typically >100 μm) to a reduced range of 5-50 μm through photolithographic patterning. This parameter change is achieved by controlling photoresist coating thickness, exposure conditions, and etching parameters, thereby maximizing the usable wafer area and increasing the number of dice that can be produced per wafer.
2Quantity of substance
If smaller scribe lines are used to increase gross die number, then wafer space utilization improves, but the difficulty of precise patterning and etching increases
Solution Approach 1:
The patent replaces mechanical or laser-based dicing methods with a photolithographic patterning process followed by plasma etching. This substitution enables precise control of scribe line width at the micro-scale (5-50 μm), significantly reducing the scribe line area and increasing the gross die number per wafer.
Solution Approach 2:
The patent employs a periodic process sequence: photoresist coating → photolithographic exposure → photoresist development → plasma etching → photoresist stripping. This periodic action allows precise control of the scribe line dimensions through controlled exposure and etching cycles, achieving the required patterning precision for narrow scribe lines while maintaining manufacturability.
3Area of stationary object
If bonding pads are strategically placed and scribe lines are arranged along or through pads, then wafer space optimization is achieved, but the complexity of the dicing process increases
Solution Approach 1:
The patent performs preliminary action by pre-defining the optimal arrangement of bonding pads and scribe lines during the photolithographic patterning step. The scribe lines are strategically positioned to pass through or along bonding pads, and the photoresist is patterned accordingly before etching. This preliminary planning and positioning enable efficient wafer space utilization while maintaining a manageable process sequence.
Solution Approach 2:
The photolithographic patterning process serves multiple functions: it defines the scribe line locations, positions the bonding pads optimally, and prepares the pattern for plasma etching. This multi-functional approach consolidates several steps into one versatile process, reducing overall process complexity while achieving optimized wafer space utilization and strategic pad placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the gross die number by reducing the scribe line width and optimizing wafer space, enabling more efficient semiconductor dice separation and packaging, such as in T-contact chip scale packages.
Implementation Method 1
A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line
Implementation Method 2
the scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern
Data Source
AI summary
The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.