Wafer Dicing via Plasma Etching and Scribe Line Segmentation

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Solution Overview

Problem

The shrinking critical dimension of semiconductor devices increases manufacturing costs due to longer wafer dicing times in mechanical dicing processes, and plasma dicing is impeded by non-dry-etchable materials in scribe lines, which can damage dies during byproduct removal.

Innovation Solution

A method of wafer dicing that removes the scribe line structure in multiple stages, using lithography and etching processes to isolate the test device, and then employing plasma dicing to disconnect the scribe line structure from dies without directly removing the test device, allowing for efficient separation and reduced manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If plasma dicing process is applied to reduce wafer dicing time, then productivity is improved, but the process is impeded when scribe lines contain non-dry-etchable materials like Al

Engineering Contradiction:
Improvewafer dicing timeVSAvoidprocess feasibility
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The scribe line structure is divided into two parts: the test device portion containing Al and the insulating layer portion. The insulating layer is selectively removed in advance, allowing plasma dicing to proceed without being impeded by the Al-containing test device, thus enabling both high productivity and process feasibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The insulating layer surrounding the test device is removed before the plasma dicing process. This preliminary action eliminates the barrier that would prevent plasma dicing, allowing the subsequent dicing to proceed efficiently without impediment from non-dry-etchable materials

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If additional solution process is applied to remove byproduct, then the barely etchable material is removed, but the dies are damaged

Engineering Contradiction:
Improvebyproduct removalVSAvoiddie integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The insulating layer containing the barely etchable material is extracted and removed in advance, before plasma dicing. This eliminates the need for additional solution processes that would damage the dies, as the problematic material is already removed and will not generate harmful byproducts during dicing

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If mechanical dicing or laser dicing is applied, then the wafer can be diced, but the die singulation time is much longer

Engineering Contradiction:
Improvedicing capabilityVSAvoiddie singulation time
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The insulating layer is removed in advance through lithography and etching processes, preparing the wafer for rapid plasma dicing. This preliminary preparation enables the subsequent plasma dicing to proceed much faster than mechanical or laser dicing, significantly reducing die singulation time while maintaining ease of manufacture

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method significantly shortens the die singulation time in plasma dicing compared to laser or mechanical dicing, lowering manufacturing costs while avoiding damage to barely etchable materials.

Implementation Method 1

a plasma dicing process

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS10515853B1Method of wafer dicing
Publication Date: 2019.12.24 WINBOND ELECTRONICS CORP
  • US10515853B1 patent drawing
  • US10515853B1 patent drawing
  • US10515853B1 patent drawing

AI summary

A method of wafer dicing is provided. The method of wafer dicing includes: providing a wafer, wherein the wafer includes a substrate, dies formed in and over the substrate and a scribe line structure located in a scribe line region between adjacent dies; removing a portion of the scribe line structure around a test device in the scribe line structure; attaching a front side of the wafer with a first tape; removing a portion of the substrate overlapping with the scribe line region from a back side of the wafer; attaching the back side of the wafer with a second tape; and removing the first tape along with the remaining portion of the scribe line structure attached thereon, leaving the dies separately attached on the second tape.