Wafer Dicing Using Segmented Trenches and Polyimide
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Solution Overview
Problem
Current wafer-level packaging methods face challenges in achieving smooth chip edges and maximizing die yield due to limitations in dicing techniques, particularly in reducing scribe width and minimizing wafer breakage during the process.
Innovation Solution
The method involves forming trenches between integrated circuit regions, applying a photosensitive polyimide layer with breaking delimitations, and using a flexible dicing foil to facilitate precise dicing and separation of semiconductor chips, allowing for underbump metallizations and bump contacts before grinding, which reduces scribe width and preserves smooth edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional dicing methods are used, then wafer-level packaging can be achieved, but scribe width is large (80 µm) and die yield is reduced
Solution Approach 1:
The scribe street is segmented into discrete trenches that extend partially through the substrate thickness, creating separation zones between adjacent dies. This segmentation allows the polyimide layer to be applied continuously across the wafer while the trenches provide physical separation, enabling reduced scribe width without compromising die isolation or yield.
Solution Approach 2:
The solution transitions from a two-dimensional surface-level dicing approach to a three-dimensional trench-based method. Trenches extend vertically into the substrate (but not completely through), creating depth-based separation that allows narrower surface-wide scribe streets while maintaining effective die isolation.
2Shape
If dicing is performed before grinding, then smooth chip edges can be achieved, but wafer breakage risk increases during the process
Solution Approach 1:
Trenches are formed in the substrate before the dicing step, creating pre-defined separation zones that guide the dicing process. This preliminary structuring allows subsequent dicing to follow predetermined paths with reduced stress concentration, minimizing wafer breakage while ensuring smooth edges at chip boundaries.
Solution Approach 2:
The polyimide layer is applied across the entire wafer surface, including over the trenches and scribe streets, before dicing. This continuous polyimide layer acts as a cushioning and support structure during the dicing process, distributing mechanical stresses and preventing wafer breakage while allowing clean separation at the trench locations.
3Strength
If the polyimide layer is applied as a continuous layer, then wafer strength is improved, but separation of individual chips becomes difficult
Solution Approach 1:
While the polyimide layer is applied continuously across the wafer to maintain strength, the underlying trenches create natural separation zones. The continuous polyimide provides mechanical support and strength during processing, while the trenches below enable clean separation of individual chips when dicing is performed, resolving the contradiction between continuity and separability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the combination of wafer-level chip-scale packaging with trench dicing before grinding, reducing scribe width from 80 µm to 15 µm, maximizing die yield, and allowing wafers to be processed at full thickness, thereby minimizing breakage and ensuring smooth chip edges.
Implementation Method 1
The polyimide layer is photosensitive, and the breaking delimitations are formed using photolithography
Data Source
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Figure 5~6
AI summary
A semiconductor substrate (1) is provided with integrated circuits. Dicing trenches (7) are formed in the substrate (1) between the integrated circuits, a polyimide layer (8) spanning the trenches (7) is applied above the integrated circuits, a tape layer (14) is applied above the polyimide layer (8), and a layer portion of the substrate (1) is removed from the substrate side (17) opposite the tape layer (14), until the trenches (7) are opened and dicing of the substrate (1) is thus effected. The polyimide layer (8) is severed in sections (18) above the trenches (7) when the tape layer (14) is removed. The semiconductor chip is provided with a cover layer (11) laterally confining the polyimide layer (8) near the trenches (7), in particular for forming breaking delimitations (9).