Wafer Dicing Skip-Line Control for Void-Induced Chipping

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Solution Overview

Problem

Void generation at the bonding interface of bonded semiconductor wafers can lead to chipping during the dicing process, contaminating the dicing device and complicating subsequent processing steps.

Innovation Solution

A semiconductor manufacturing apparatus and method that includes a storage device for storing location information of dicing lines and skip lines on a semiconductor wafer, and a cutter configured to cut the wafer along specified dicing lines while avoiding skip lines, thereby preventing chipping due to voids.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dicing is performed on bonding wafers with voids at the bonding interface, then semiconductor chips can be produced, but chipping occurs during the dicing process

Engineering Contradiction:

Improvechip productionVSAvoidchip integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system performs preliminary detection of voids at the bonding interface before the dicing process. By identifying void locations in advance using inspection data, the dicing process can be adjusted to avoid cutting through void-containing regions, thereby preventing chipping while maintaining chip production

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from void detection inspections to dynamically adjust dicing parameters. The detection results about void locations are fed back to control the dicing process, enabling real-time adjustments to cutting paths or parameters to avoid problematic areas and prevent chipping

Inventive Principle:

Principle #23Feedback

2Productivity

If dicing is performed through void regions, then complete wafer processing is achieved, but contamination of the dicing device occurs

Engineering Contradiction:

Improvewafer processing completionVSAvoiddevice contamination

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The system performs preliminary detection of voids before dicing to identify regions that would generate contamination. By detecting void locations in advance, the system can adjust the dicing path to bypass void regions, preventing chip fragmentation and subsequent device contamination while still completing wafer processing

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system converts the harmful effect of voids (which cause chipping and contamination) into a useful detection target. By detecting void locations and using this information to adjust the dicing process, the system transforms the potential harm into an opportunity to optimize the cutting path and prevent contamination

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20250087502A1Semiconductor manufacturing apparatus and method for manufacturing semiconductor device

Publication Date: 2025.03.13 KIOXIA CORP

AI summary

A semiconductor manufacturing apparatus includes a storage device configured to store first location information of a plurality of first lines on a first surface of a semiconductor wafer to be cut, and further store second location information of a second line not to be cut among the plurality of first lines; and a cutter configured to cut the semiconductor wafer along one or more of the plurality of first lines other than the second line. The semiconductor wafer is configured to be cut into a plurality of semiconductor chips.