Semiconductor Wafer Dicing Layout for Warpage Stress Release

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Solution Overview

Problem

Chipping or cracking occurs during the dicing process of semiconductor wafers due to inherent stress release when warped or distorted wafers are fixed to a flat surface, leading to unstable dicing conditions and potential defects.

Innovation Solution

The semiconductor wafer is diced along multiple directions with at least one dicing line overlapping a film formation pattern, allowing stress release only at specific warped or distorted portions, reducing chipping and cracking by designating the film formation pattern's location and minimizing blade clogging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a warped or distorted wafer is pressed or fixed on a flat surface of a chuck table, then the wafer can be held in position for dicing, but stress existing in the wafer is released within an effective area causing chipping or cracks

Engineering Contradiction:

Improvewafer fixingVSAvoidchip quality

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The patent applies local quality by positioning the dicing line to overlap with the film formation pattern only in specific local areas where warpage or distortion is present. This allows stress release to occur locally at the warped portions rather than across the entire effective area, preventing chipping and cracks while maintaining chip quality.

Inventive Principle:

Principle #3Local quality

2Productivity

If dicing is performed with a blade on a warped wafer, then chips can be cut from the wafer, but the impact on the wafer is large causing unstable dicing conditions

Engineering Contradiction:

Improvedicing throughputVSAvoiddicing stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-positioning the dicing line to overlap with the film formation pattern before the dicing process begins. This preliminary configuration ensures that stress release occurs in a controlled manner during dicing, stabilizing the cutting process and preventing chipping or cracks even when warpage varies between wafers.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If the dicing line is positioned to overlap the film formation pattern, then stress release is controlled and chipping is suppressed, but the dicing process becomes more complex

Engineering Contradiction:

Improvechip qualityVSAvoiddicing process

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies universality by utilizing the existing film formation pattern, which is already present on the wafer from previous manufacturing steps, to simultaneously serve as a guide for dicing line positioning. This multi-functional use of the film pattern simplifies the overall process by eliminating the need for separate warpage measurement and dicing line adjustment steps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12575372B2Semiconductor wafer and method for manufacturing semiconductor wafer

Publication Date: 2026.03.10 MITSUBISHI ELECTRIC CORP

AI summary

A semiconductor wafer is diced along a plurality of dicing lines in a first direction and a second direction different from the first direction so that a chip is cut out from an effective area. The semiconductor water includes a film formation pattern. At least one dicing line included in the plurality of dicing lines is an on-pattern dicing line which overlaps the film formation pattern in its entire or partial length.