Wafer Dicing with Plasma-Etched Scribe Street Test Device Removal
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Solution Overview
Problem
Existing wafer dicing methods, such as mechanical cleaving, laser ablation, and plasma etching, face challenges in efficiently removing test devices from semiconductor wafers without causing damage or increasing costs, especially when test devices are present in scribe streets.
Innovation Solution
A method involving the application of a photoresist layer on the non-device side of a semiconductor wafer, photolithographic processes to create aligned openings, followed by plasma etching to form narrow trenches, and using a tape to remove test devices by detaching them from the wafer during tape removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mechanical cleaving or laser ablation is used for wafer dicing, then the dicing process can be completed, but test devices in scribe streets cannot be efficiently removed and mechanical stress or damage may occur
Solution Approach 1:
The patent replaces mechanical cleaving and laser ablation with plasma etching to remove test devices. The plasma etching process uses reactive ions to chemically etch away the test devices in scribe streets without mechanical contact, eliminating mechanical stress and damage while efficiently removing test devices that would otherwise require complex mechanical removal processes
Solution Approach 2:
The patent changes the physical and chemical parameters of the etching process by using plasma chemistry with controlled gas flows and power settings. This allows selective removal of test devices based on their material composition and geometry, enabling efficient test device removal without affecting the semiconductor circuits while avoiding mechanical stress
2Manufacturing precision
If plasma etching is used to create narrow trenches, then etching precision is improved, but test device removal becomes more difficult
Solution Approach 1:
The patent applies preliminary action by first forming a photoresist mask with openings positioned over the test devices before plasma etching. This mask guides the plasma etching to create narrow trenches that precisely define the test device boundaries, and the subsequent tape removal step automatically extracts the etched test devices, solving both precision and ease of removal
Solution Approach 2:
The patent introduces a tape intermediary that is applied over the photoresist mask and wafer. During tape removal, the tape acts as a mediator to automatically extract the plasma-etched test devices from the scribe streets, combining precise plasma etching with easy test device removal through a single automated step
3Manufacturing precision
If test devices are removed separately before dicing, then dicing quality is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple steps into a single integrated process: photoresist coating, pattern formation, plasma etching of test devices, and tape removal all occur in sequence without separate manual intervention. The plasma etching and tape removal steps are combined such that test device removal is automatically achieved during the standard dicing process, reducing manufacturing complexity while maintaining high dicing quality
Solution Approach 2:
The patent implements self-service by designing the process so that standard dicing equipment and materials (photoresist, plasma etcher, tape) perform the test device removal function automatically. The plasma etching process selectively removes test devices based on their location and material properties, and the tape removal step automatically extracts them, eliminating the need for specialized test device removal equipment or procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates efficient and cost-effective removal of test devices during wafer dicing, ensuring precise etching and minimizing mechanical stress, while allowing for the formation of semiconductor packages with improved die quality and reduced costs.
Implementation Method 1
performing a photolithographic process to form an opening in the photoresist layer
Implementation Method 2
plasma etching through the semiconductor wafer by way of the opening in the photoresist layer
Data Source
AI summary
In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer by way of the opening in the photoresist layer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape from device sides of the first and second semiconductor dies, wherein removing the tape includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member. The method also comprises covering the first semiconductor die with a mold compound, the conductive member exposed to an exterior surface of the mold compound.