Wafer Dicing and Test Packaging for Semiconductor Testing
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Solution Overview
Problem
Existing test apparatuses for semiconductor wafers require numerous costly wires and are difficult to adjust, and testing chips in commercial packages incur high costs due to complex package configurations.
Innovation Solution
A manufacturing system that dices semiconductor wafers into individual devices, packages them in test packages using flexible substrates for easy handling and testing, and then transfers them to commercial packages, reducing the need for complex wire connections and adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a probe card is used to test multiple devices on a wafer, then testing efficiency is improved, but the cost increases due to numerous wires required for the probe card
Solution Approach 1:
The invention divides the testing process into two stages: wafer-level screening using a simple probe card, and individual device testing after dicing. This segmentation allows the complex wire connections to be eliminated in favor of simpler post-dice testing methods, resolving the contradiction between testing efficiency and wire complexity
Solution Approach 2:
The invention performs preliminary testing on the wafer before dicing to identify and separate defective devices. This preliminary action eliminates the need for complex wire connections during individual device testing, as only passing devices require detailed testing with fewer connections
2Productivity
If a probe card is used for wafer testing, then multiple devices can be tested simultaneously, but adjusting the relative positions of the wafer and probe card becomes difficult
Solution Approach 1:
The invention segments the testing process into wafer-level screening and individual device testing. The wafer-level screening uses a fixed probe card configuration for parallel testing, while subsequent individual device testing uses simpler positioning methods, thereby resolving the position adjustment difficulty while maintaining parallel testing capability
3Adaptability or versatility
If chips are tested in commercial packages, then package compatibility is improved, but the cost increases due to complex package configurations
Solution Approach 1:
The invention performs testing before final commercial packaging using temporary test packages or wafer-level testing. This preliminary action allows compatibility verification without requiring the complex commercial package configuration, thereby reducing costs while maintaining adaptability
Solution Approach 2:
The invention introduces an intermediate testing stage using simplified test packages or wafer-level testing as a mediator between manufacturing and final packaging. This intermediary approach allows compatibility testing without the complexity of final package configurations
Data Source
AI summary
Provided is a test apparatus for testing a device under test, including a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test, a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package, a testing section that tests the devices under test packaged in the test packages, a removing section that removes the devices under test that have been tested from the test packages, and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.