Wafer Dicing Layout for Plasma Etch Test Device Removal
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Solution Overview
Problem
Existing wafer dicing methods, such as mechanical cleaving, laser ablation, and stealth dicing, produce semiconductor dies of lower quality, while plasma etching is hindered by the difficulty in removing test devices from semiconductor wafers, leading to increased costs and inefficiencies.
Innovation Solution
A method involving the application of a photoresist layer on the non-device side of a semiconductor wafer, followed by photolithographic processes to create vertically aligned openings, and subsequent plasma etching to form narrow trenches aligned with test devices, allowing for efficient removal of test devices using a tape during the dicing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plasma etching is used to dice semiconductor wafers, then manufacturing precision and quality of semiconductor dies are improved, but the difficulty of removing test devices increases
Solution Approach 1:
The patent applies preliminary action by forming openings in the photoresist layer that are vertically aligned with the scribe streets and test devices before plasma etching. This pre-alignment ensures that test devices are exposed through the openings during etching, allowing them to be automatically removed when the tape is peeled off after dicing, thus resolving the contradiction between achieving high precision plasma etching and the difficulty of test device removal.
2Device complexity
If traditional mechanical cleaving or laser ablation is used for wafer dicing, then test device removal is easier, but manufacturing precision and quality of semiconductor dies deteriorate
Solution Approach 1:
The patent merges two previously separate processes into one unified plasma etching process: (1) the dicing of the wafer into individual dies, and (2) the removal of test devices from scribe streets. By aligning openings with both the scribe streets and test devices, and using a single plasma etching step, the patent achieves both high precision cutting and automatic test device removal, eliminating the need to choose between mechanical methods (easy removal but low precision) and plasma etching (high precision but difficult removal).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates the efficient and cost-effective removal of test devices during wafer dicing, enhancing plasma etching precision and reducing mechanical stress, while producing semiconductor dies with a larger device side area and minimizing design space and costs.
Implementation Method 1
performing a photolithographic process to form an opening in the photoresist layer
Implementation Method 2
plasma etching through the semiconductor wafer by way of the opening in the photoresist layer
Data Source
AI summary
In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape, which includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member. The method also comprises covering the first semiconductor die with a mold compound.