Wafer Dicing Trenches for Chip Package Alignment

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Solution Overview

Problem

Conventional chip packaging methods are time-consuming and costly, and prone to alignment offset issues due to the complexity of the process steps involved in dicing and packaging semiconductor dies.

Innovation Solution

A method involving a wafer with conductive bumps, where trenches are formed, insulation layers are applied, and a surface treatment layer is added, followed by thinning and further insulation, allowing for precise dicing along trenches to create chip packages, reducing process time and cost while preventing alignment offset.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional one-by-one packaging method is used, then packaging precision can be maintained, but processing time and cost increase significantly

Engineering Contradiction:

Improvepackaging speedVSAvoidprocessing time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The wafer is diced into multiple trenches to divide the packaging process into separate sections, allowing simultaneous processing of multiple dies while maintaining individual packaging precision through the insulation layer separation

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first insulation layer is formed on the upper surface and in the trenches before the dicing process, preparing the structural framework in advance to prevent alignment offset during subsequent packaging operations

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If wafer is thinned to expose first insulation layer, then dicing precision is improved, but wafer strength decreases

Engineering Contradiction:

Improvedicing precisionVSAvoidwafer strength

Core Design Contradiction:

Manufacturing precisionVSStrength

Solution Approach 1:

The second insulation layer is formed on the lower surface of the wafer before the thinning process to provide structural support and cushioning, preventing wafer breakage during thinning while allowing precise exposure of the first insulation layer

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Manufacturing precision

If multiple process steps are added for precision, then alignment accuracy is improved, but device complexity increases

Engineering Contradiction:

Improvealignment accuracyVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The insulation layer formation and dicing processes are merged into an integrated sequence where the first insulation layer is formed, the wafer is thinned to expose it, and then dicing is performed along the exposed insulation layer, simplifying the overall process while maintaining precision

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10665509B2Method for manufacturing chip packages

Publication Date: 2020.05.26 COMCHIP TECH

AI summary

A method for manufacturing chip package includes the steps below. A wafer having an upper surface and a lower surface opposite thereto is provided, in which conductive bumps are disposed on the upper surface. The upper surface of the wafer is diced to form trenches. A first insulation layer exposing the conductive bumps is formed on the upper surface and in the trenches. A surface treatment layer is formed on the conductive bumps, and a top surface of the surface treatment layer is higher than that of the first insulation layer. The wafer is thinned from the lower surface toward the upper surface to expose the first insulation layer in the trenches. A second insulation layer is formed below the lower surface. The first and second insulation layers are diced along a center of each trench to form chip packages.