Silicon Wafer Die Integration with Multi-Level Redistribution
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high performance and compact packaging of multiple functional dies on a single silicon wafer due to the complexity of integrating diverse functional components and ensuring efficient communication between them without degrading data transmission efficiency.
Innovation Solution
The integration of a system-on-silicon wafer (SoSW) device is achieved by forming a plurality of functional dies of different types on a single silicon wafer using distinct mask sets and forming redistribution and fan-out structures to provide local, semi-global, and global interconnects, allowing for efficient communication between dies without the need for complex I/O interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple functional dies are integrated on a single silicon wafer, then integration density and compactness are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the silicon wafer into multiple discrete functional dies, each performing different functions. These segmented dies are then individually processed and integrated with redistribution structures, allowing complex functionality to be achieved through modular assembly rather than monolithic design
Solution Approach 2:
The patent introduces vertical stacking of redistribution structures (multiple metallization layers, dielectric layers, and via structures) to achieve three-dimensional integration. This dimensional transition from planar to vertical interconnects enables compact packaging while managing the complexity of multiple functional dies
2Adaptability or versatility
If functional dies are singulated from substrates and placed on carrier substrates, then packaging flexibility is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary processing of functional dies on their original substrates before singulation, including forming conductive structures and dielectric layers. This preliminary action simplifies subsequent assembly steps by pre-configuring the dies with necessary interconnect structures
Solution Approach 2:
The patent introduces carrier substrates as intermediary elements that temporarily hold functional dies during processing and enable subsequent integration. These carrier substrates act as mediators that simplify the handling and alignment of multiple dies during the packaging process
3Volume of moving object
If wafer level integration techniques are used, then device size is reduced, but manufacturing sophistication requirements increase
Solution Approach 1:
The patent employs universal manufacturing processes that can handle multiple die types and functions on a single wafer. The same fabrication techniques (deposition, etching, CMP) are applied across different functional regions, enabling wafer-level processing without requiring specialized equipment for each die type
Solution Approach 2:
The patent utilizes parameter changes in the manufacturing process, such as adjusting deposition thicknesses, etch selectivities, and CMP polishing rates, to accommodate different functional die requirements while maintaining wafer-level processing. This enables flexible manufacturing of diverse components using standardized processes
Data Source
AI summary
Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.