Wafer-Level Die Testing via Removable RDL Series Connections
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Solution Overview
Problem
Existing semiconductor testing structures fail to provide a robust check of performance and yield, especially as the number of dies per wafer increases, and they are limited by manufacturing time and cost, with insufficient area for testing pads, leading to inadequate early detection of device failures.
Innovation Solution
Implementing a series connection of devices for testing using redistribution structures (RDLs) to perform semiconductor device tests on multiple dies, allowing for sequential execution and generating a bit sequence indicating overall and individual die outcomes, with the option to remove RDLs post-testing to continue manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of dies per wafer is increased, then integration density and productivity are improved, but the available area for testing pads decreases and measurement precision deteriorates
Solution Approach 1:
The patent transitions from two-dimensional pad layout on individual dies to a three-dimensional stacked architecture where testing structures are distributed across multiple vertical layers. This allows testing pads to be arranged in the vertical dimension (through interconnect vias between dies) rather than competing for horizontal surface area, enabling high-density die stacking while maintaining adequate testing pad area on each die.
Solution Approach 2:
The testing function is segmented across multiple dies in the stack rather than requiring all testing pads on a single die. Each die contributes a portion of the overall testing infrastructure through its interconnect structures, distributing the testing load and pad requirements across the vertical stack, thereby reducing the area burden on any individual die.
2Reliability
If traditional testing methods are used on stacked dies, then device functionality is verified, but manufacturing time increases and productivity decreases
Solution Approach 1:
The testing structures are formed as part of the interconnect architecture during the normal stacking process, rather than being added as a separate post-stack modification step. The via structures that connect dies are simultaneously configured to provide testing access, so that when dies are stacked, the testing capability is already in place and ready for use, eliminating additional manufacturing steps.
Solution Approach 2:
The interconnect via structures serve dual functions: they provide electrical connection between stacked dies for normal operation, and they simultaneously serve as testing access points for verifying device functionality. This multi-functionality eliminates the need for separate dedicated testing structures, reducing manufacturing complexity and time.
3Measurement precision
If sufficient area is allocated for testing pads on each die, then measurement precision and reliability are improved, but the number of dies per wafer decreases and productivity worsens
Solution Approach 1:
Testing access is extended into the vertical dimension through interconnect vias that penetrate through multiple die layers. This allows testing signals to reach internal circuitry through the stack height rather than requiring large pad areas on the die surface, enabling high die density while maintaining adequate testing capability through the third dimension.
Solution Approach 2:
The interconnect via structures act as intermediaries that provide testing access to internal circuitry without requiring direct surface mounting of large testing pads. These vias serve as conduits that bridge the surface and internal circuit layers, enabling precise measurement of internal device performance through compact surface structures.
Data Source
AI summary
A plurality of devices for testing, connected in series using one or more redistribution layers (RDLs), are used to perform a semiconductor device test on a plurality of dies. As a result, the semiconductor device test may support thousands of gross dies per wafer or greater (e.g., 10,000 dies or greater). Furthermore, the RDL(s) may be removed after use. In some implementations, the devices for testing corresponding to the dies may execute the semiconductor device test sequentially. Accordingly, test data may be generated and may include a bit sequence, where a first bit in the bit sequence indicates an overall outcome for the test and one or more subsequent bits in the bit sequence indicate respective outcomes for each semiconductor dies or for each line of the semiconductor device test.