Wafer Package Dimension Conversion for Nominal Tool Compatibility

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Solution Overview

Problem

Existing processing equipment for electro-photonic circuit packages is often configured for specific wafer dimensions, limiting its adaptability to wafers of different sizes and shapes, leading to costly re-tooling and incompatibility issues.

Innovation Solution

Techniques for modifying wafer dimensions to conform to nominal sizes compatible with processing equipment, such as using peripheral overmolds or peripheral wafers with cutouts, allowing existing equipment to process wafers of varying dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If processing equipment is configured for specific wafer dimensions, then processing precision is maintained, but adaptability to different wafer sizes deteriorates

Engineering Contradiction:

Improveprocessing precisionVSAvoidadaptability to different wafer sizes

Core Design Contradiction:

Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

A peripheral wafer with a cutout is introduced as an intermediary component. The cutout is sized to match the actual wafer dimensions, while the peripheral wafer itself matches the nominal dimensions of the processing equipment. This intermediary allows the equipment to process wafers of varying sizes without re-tooling, as the cutout portion is removed after processing.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The solution segments the wafer handling into two distinct parts: the peripheral wafer (which interfaces with the processing equipment) and the actual wafer (which fits within the cutout). This segmentation allows each part to serve its specific function - the peripheral wafer maintains compatibility with equipment while the cutout accommodates the actual processing target.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If processing equipment is re-tooled for different wafer dimensions, then adaptability improves, but cost and complexity increase

Engineering Contradiction:

Improveadaptability to different wafer sizesVSAvoidre-tooling cost and complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The peripheral wafer design provides universal compatibility with processing equipment for multiple wafer sizes. Instead of creating different processing equipment for different wafer dimensions, a single peripheral wafer template can accommodate various actual wafers by simply changing the cutout dimensions, making the system multi-functional without increasing equipment complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If peripheral overmolds are used to modify wafer dimensions, then compatibility with processing equipment improves, but manufacturing complexity increases

Engineering Contradiction:

Improvecompatibility with processing equipmentVSAvoidmanufacturing complexity

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The peripheral wafer with cutout acts as a disposable or temporary structure that is removed after processing. This approach avoids the need for permanent, complex modifications to the processing equipment or the actual wafer. The peripheral wafer serves its purpose during processing and is then discarded, simplifying the overall manufacturing approach.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS20250370201A1Converting processing dimensions of a wafer package

Publication Date: 2025.12.04 SICILY MERGER SUB II INC

AI summary

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing wafers having circuit packages formed thereon. Techniques described herein related to modifying a dimension of wafers in order that the wafers conform to a nominal dimension, such that the wafers may be implemented in connection with processing equipment that is specifically configured to operate on wafers of the nominal dimension.