Wafer Directional Indicators for Aligning Angled Semiconductor Features

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Solution Overview

Problem

Conventional semiconductor fabrication techniques face challenges in increasing transistor density due to alignment limitations with interconnect structures, leading to compromised performance and manufacturing complexity, especially when attempting to incorporate angled semiconductor structures.

Innovation Solution

The use of directional indicators, such as flats and notches, on a wafer to align angled semiconductor features during photolithography, allowing for precise orientation and increased transistor density without the need for complex process adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional alignment techniques are used with interconnect structures, then manufacturing process is simpler, but transistor density increases are limited and performance is compromised

Engineering Contradiction:
Improvetransistor densityVSAvoidalignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces directional indicators (flats and notches) as intermediary reference features on the wafer that mediate between the photolithography alignment system and the interconnect structures. These indicators serve as a common reference framework that enables precise alignment of angled semiconductor features without requiring complex adjustments to the interconnect structure alignment process itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The directional indicators are formed on the wafer before the photolithography processes that create angled semiconductor features. This preliminary establishment of reference features allows subsequent alignment operations to proceed with higher precision, enabling increased transistor density without compromising the alignment of interconnect structures.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If angled semiconductor structures are incorporated to increase density, then transistor density improves, but manufacturing complexity increases

Engineering Contradiction:
Improvetransistor densityVSAvoidprocess complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The directional indicators act as intermediary reference features that simplify the manufacturing of angled semiconductor structures. By providing a clear geometric reference system (flats and notches), the patent reduces the complexity of aligning angled features during photolithography, making the incorporation of high-density angled structures more manufacturable.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs asymmetric geometric features (flats and notches) on the circular wafer to establish directional references. This asymmetry provides unambiguous orientation information that simplifies the alignment process for angled semiconductor structures, reducing process complexity while enabling higher transistor density.

Inventive Principle:
Principle #4Asymmetry

3Manufacturing precision

If multiple directional indicators are added to the wafer, then alignment precision improves, but device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidwafer structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the directional indication function into multiple distinct indicators (first flat, second flat, first notch, second notch) positioned at different locations and orientations on the wafer. This segmentation provides comprehensive angular references that improve alignment precision for various photolithography steps while keeping each individual indicator simple in form.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The directional indicators serve multiple functions: they provide reference for wafer orientation, establish angular references for photolithography alignment, and enable precise positioning of angled semiconductor features. This multi-functionality justifies their inclusion despite the slight increase in wafer structure complexity, as they eliminate the need for separate alignment mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240071955A1Full wafer device with multiple directional indicators
Publication Date: 2024.02.29 INTEL CORP
  • US20240071955A1 patent drawing
  • US20240071955A1 patent drawing
  • US20240071955A1 patent drawing

AI summary

Described herein is full wafer device that includes a computing logic formed over a substrate and two directional indicators formed in the substrate. The computing logic is arranged as a plurality of dies having a first die edge direction and a second die edge direction perpendicular to the first die edge direction. The computing logic further includes an angled feature extending in a feature direction, the feature direction different from the first die edge direction and the second die edge direction. The first directional indicator formed in the substrate indicates the first die edge direction. The second directional indicator formed in the substrate indicates the feature direction.